ilo: add support for indirect access of CONST in FS

[mesa.git] / src / gallium / drivers / radeonsi / r600_texture.c

diff --git a/src/gallium/drivers/radeonsi/r600_texture.c b/src/gallium/drivers/radeonsi/r600_texture.c
index d54655441a004618ea3cb9f08f3ef0694a5a7e2c..8992f9a1fa29b2683b091fc09c29e04d194e8673 100644 (file)
--- a/src/gallium/drivers/radeonsi/r600_texture.c
+++ b/src/gallium/drivers/radeonsi/r600_texture.c
@@ -47,7 +47,6 @@ static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_t
                                &transfer->box);
 }
 
-
 /* Copy from a transfer's staging texture to a full GPU one. */
 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
 {
@@ -55,7 +54,7 @@ static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600
        struct pipe_resource *texture = transfer->resource;
        struct pipe_box sbox;
 
-       u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox);
+       u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
 
        ctx->resource_copy_region(ctx, texture, transfer->level,
                                  transfer->box.x, transfer->box.y, transfer->box.z,
@@ -152,12 +151,12 @@ static int r600_init_surface(struct r600_screen *rscreen,
 
        if (!is_flushed_depth && is_depth) {
                surface->flags |= RADEON_SURF_ZBUFFER;
-
                if (is_stencil) {
                        surface->flags |= RADEON_SURF_SBUFFER |
                                RADEON_SURF_HAS_SBUFFER_MIPTREE;
                }
        }
+       surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
        return 0;
 }
 
@@ -235,7 +234,6 @@ static void *si_texture_transfer_map(struct pipe_context *ctx,
 {
        struct r600_context *rctx = (struct r600_context *)ctx;
        struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
-       struct pipe_resource resource;
        struct r600_transfer *trans;
        boolean use_staging_texture = FALSE;
        struct radeon_winsys_cs_handle *buf;
@@ -295,42 +293,52 @@ static void *si_texture_transfer_map(struct pipe_context *ctx,
                                         level, level,
                                         box->z, box->z + box->depth - 1);
                trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
+               trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
                trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
 
                trans->staging = &staging_depth->resource.b.b;
        } else if (use_staging_texture) {
-               resource.target = PIPE_TEXTURE_2D;
+               struct pipe_resource resource;
+               struct r600_resource_texture *staging;
+
+               memset(&resource, 0, sizeof(resource));
                resource.format = texture->format;
                resource.width0 = box->width;
                resource.height0 = box->height;
                resource.depth0 = 1;
                resource.array_size = 1;
-               resource.last_level = 0;
-               resource.nr_samples = 0;
                resource.usage = PIPE_USAGE_STAGING;
-               resource.bind = 0;
                resource.flags = R600_RESOURCE_FLAG_TRANSFER;
-               /* For texture reading, the temporary (detiled) texture is used as
-                * a render target when blitting from a tiled texture. */
-               if (usage & PIPE_TRANSFER_READ) {
-                       resource.bind |= PIPE_BIND_RENDER_TARGET;
-               }
-               /* For texture writing, the temporary texture is used as a sampler
-                * when blitting into a tiled texture. */
-               if (usage & PIPE_TRANSFER_WRITE) {
-                       resource.bind |= PIPE_BIND_SAMPLER_VIEW;
+
+               /* We must set the correct texture target and dimensions if needed for a 3D transfer. */
+               if (box->depth > 1 && util_max_layer(texture, level) > 0)
+                       resource.target = texture->target;
+               else
+                       resource.target = PIPE_TEXTURE_2D;
+
+               switch (resource.target) {
+               case PIPE_TEXTURE_1D_ARRAY:
+               case PIPE_TEXTURE_2D_ARRAY:
+               case PIPE_TEXTURE_CUBE_ARRAY:
+                       resource.array_size = box->depth;
+                       break;
+               case PIPE_TEXTURE_3D:
+                       resource.depth0 = box->depth;
+                       break;
+               default:;
                }
                /* Create the temporary texture. */
-               trans->staging = ctx->screen->resource_create(ctx->screen, &resource);
-               if (trans->staging == NULL) {
+               staging = (struct r600_resource_texture*)ctx->screen->resource_create(ctx->screen, &resource);
+               if (staging == NULL) {
                        R600_ERR("failed to create temporary texture to hold untiled copy\n");
                        pipe_resource_reference(&trans->transfer.resource, NULL);
                        FREE(trans);
                        return NULL;
                }
 
-               trans->transfer.stride = ((struct r600_resource_texture *)trans->staging)
-                                       ->surface.level[0].pitch_bytes;
+               trans->staging = &staging->resource.b.b;
+               trans->transfer.stride = staging->surface.level[0].pitch_bytes;
+               trans->transfer.layer_stride = staging->surface.level[0].slice_size;
                if (usage & PIPE_TRANSFER_READ) {
                        r600_copy_to_staging_texture(ctx, trans);
                        /* Always referenced in the blit. */
@@ -345,7 +353,7 @@ static void *si_texture_transfer_map(struct pipe_context *ctx,
        if (trans->staging) {
                buf = si_resource(trans->staging)->cs_buf;
        } else {
-               buf = si_resource(trans->transfer.resource)->cs_buf;
+               buf = rtex->resource.cs_buf;
        }
 
        if (rtex->is_depth || !trans->staging)
@@ -521,7 +529,11 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
 
        if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
            !(templ->bind & PIPE_BIND_SCANOUT)) {
-               array_mode = V_009910_ARRAY_1D_TILED_THIN1;
+               if (util_format_is_compressed(templ->format)) {
+                       array_mode = V_009910_ARRAY_1D_TILED_THIN1;
+               } else {
+                       array_mode = V_009910_ARRAY_2D_TILED_THIN1;
+               }
        }
 
        r = r600_init_surface(rscreen, &surface, templ, array_mode,
@@ -545,6 +557,8 @@ static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
        struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
        unsigned level = surf_tmpl->u.tex.level;
 
+       assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
+       assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
        assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
        if (surface == NULL)
                return NULL;
@@ -609,6 +623,8 @@ struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
        if (r) {
                return NULL;
        }
+       /* always set the scanout flags */
+       surface.flags |= RADEON_SURF_SCANOUT;
        return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
                                                                  stride, 0, buf, FALSE, &surface);
 }