#include "r600_resource.h"
#include "sid.h"
+/* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
+static void r600_copy_region_with_blit(struct pipe_context *pipe,
+ struct pipe_resource *dst,
+ unsigned dst_level,
+ unsigned dstx, unsigned dsty, unsigned dstz,
+ struct pipe_resource *src,
+ unsigned src_level,
+ const struct pipe_box *src_box)
+{
+ struct pipe_blit_info blit;
+
+ memset(&blit, 0, sizeof(blit));
+ blit.src.resource = src;
+ blit.src.format = src->format;
+ blit.src.level = src_level;
+ blit.src.box = *src_box;
+ blit.dst.resource = dst;
+ blit.dst.format = dst->format;
+ blit.dst.level = dst_level;
+ blit.dst.box.x = dstx;
+ blit.dst.box.y = dsty;
+ blit.dst.box.z = dstz;
+ blit.dst.box.width = src_box->width;
+ blit.dst.box.height = src_box->height;
+ blit.dst.box.depth = src_box->depth;
+ blit.mask = util_format_get_mask(src->format) &
+ util_format_get_mask(dst->format);
+ blit.filter = PIPE_TEX_FILTER_NEAREST;
+
+ if (blit.mask) {
+ pipe->blit(pipe, &blit);
+ }
+}
+
/* Copy from a full GPU texture to a transfer's staging one. */
static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
{
struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
- struct pipe_resource *texture = transfer->resource;
+ struct pipe_resource *dst = &rtransfer->staging->b.b;
+ struct pipe_resource *src = transfer->resource;
- ctx->resource_copy_region(ctx, rtransfer->staging_texture,
- 0, 0, 0, 0, texture, transfer->level,
- &transfer->box);
-}
+ if (src->nr_samples > 1) {
+ r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
+ src, transfer->level, &transfer->box);
+ return;
+ }
+ ctx->resource_copy_region(ctx, dst, 0, 0, 0, 0,
+ src, transfer->level, &transfer->box);
+}
/* Copy from a transfer's staging texture to a full GPU one. */
static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
{
struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
- struct pipe_resource *texture = transfer->resource;
+ struct pipe_resource *dst = transfer->resource;
+ struct pipe_resource *src = &rtransfer->staging->b.b;
struct pipe_box sbox;
- sbox.x = sbox.y = sbox.z = 0;
- sbox.width = transfer->box.width;
- sbox.height = transfer->box.height;
- /* XXX that might be wrong */
- sbox.depth = 1;
- ctx->resource_copy_region(ctx, texture, transfer->level,
- transfer->box.x, transfer->box.y, transfer->box.z,
- rtransfer->staging_texture,
- 0, &sbox);
-}
-
-unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
- unsigned level, unsigned layer)
-{
- unsigned offset = rtex->offset[level];
-
- switch (rtex->resource.b.b.target) {
- case PIPE_TEXTURE_3D:
- case PIPE_TEXTURE_CUBE:
- default:
- return offset + layer * rtex->layer_size[level];
- }
-}
-
-static unsigned r600_get_block_alignment(struct pipe_screen *screen,
- enum pipe_format format,
- unsigned array_mode)
-{
- struct r600_screen* rscreen = (struct r600_screen *)screen;
- unsigned pixsize = util_format_get_blocksize(format);
- int p_align;
+ u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
- switch(array_mode) {
- case V_009910_ARRAY_1D_TILED_THIN1:
- p_align = MAX2(8,
- ((rscreen->tiling_info.group_bytes / 8 / pixsize)));
- break;
- case V_009910_ARRAY_2D_TILED_THIN1:
- p_align = MAX2(rscreen->tiling_info.num_banks,
- (((rscreen->tiling_info.group_bytes / 8 / pixsize)) *
- rscreen->tiling_info.num_banks)) * 8;
- break;
- case V_009910_ARRAY_LINEAR_ALIGNED:
- p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize);
- break;
- case V_009910_ARRAY_LINEAR_GENERAL:
- default:
- p_align = rscreen->tiling_info.group_bytes / pixsize;
- break;
+ if (dst->nr_samples > 1) {
+ r600_copy_region_with_blit(ctx, dst, transfer->level,
+ transfer->box.x, transfer->box.y, transfer->box.z,
+ src, 0, &sbox);
+ return;
}
- return p_align;
-}
-
-static unsigned r600_get_height_alignment(struct pipe_screen *screen,
- unsigned array_mode)
-{
- struct r600_screen* rscreen = (struct r600_screen *)screen;
- int h_align;
-
- switch (array_mode) {
- case V_009910_ARRAY_2D_TILED_THIN1:
- h_align = rscreen->tiling_info.num_channels * 8;
- break;
- case V_009910_ARRAY_1D_TILED_THIN1:
- case V_009910_ARRAY_LINEAR_ALIGNED:
- h_align = 8;
- break;
- case V_009910_ARRAY_LINEAR_GENERAL:
- default:
- h_align = 1;
- break;
- }
- return h_align;
-}
-
-static unsigned r600_get_base_alignment(struct pipe_screen *screen,
- enum pipe_format format,
- unsigned array_mode)
-{
- struct r600_screen* rscreen = (struct r600_screen *)screen;
- unsigned pixsize = util_format_get_blocksize(format);
- int p_align = r600_get_block_alignment(screen, format, array_mode);
- int h_align = r600_get_height_alignment(screen, array_mode);
- int b_align;
-
- switch (array_mode) {
- case V_009910_ARRAY_2D_TILED_THIN1:
- b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize,
- p_align * pixsize * h_align);
- break;
- case V_009910_ARRAY_1D_TILED_THIN1:
- case V_009910_ARRAY_LINEAR_ALIGNED:
- case V_009910_ARRAY_LINEAR_GENERAL:
- default:
- b_align = rscreen->tiling_info.group_bytes;
- break;
- }
- return b_align;
-}
-
-static unsigned mip_minify(unsigned size, unsigned level)
-{
- unsigned val;
- val = u_minify(size, level);
- if (level > 0)
- val = util_next_power_of_two(val);
- return val;
-}
-
-static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
- struct r600_resource_texture *rtex,
- unsigned level)
-{
- struct pipe_resource *ptex = &rtex->resource.b.b;
- unsigned nblocksx, block_align, width;
- unsigned blocksize = util_format_get_blocksize(rtex->real_format);
- if (rtex->pitch_override)
- return rtex->pitch_override / blocksize;
-
- width = mip_minify(ptex->width0, level);
- nblocksx = util_format_get_nblocksx(rtex->real_format, width);
-
- block_align = r600_get_block_alignment(screen, rtex->real_format,
- rtex->array_mode[level]);
- nblocksx = align(nblocksx, block_align);
- return nblocksx;
+ ctx->resource_copy_region(ctx, dst, transfer->level,
+ transfer->box.x, transfer->box.y, transfer->box.z,
+ src, 0, &sbox);
}
-static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
- struct r600_resource_texture *rtex,
- unsigned level)
+static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
+ const struct pipe_box *box)
{
- struct pipe_resource *ptex = &rtex->resource.b.b;
- unsigned height, tile_height;
-
- height = mip_minify(ptex->height0, level);
- height = util_format_get_nblocksy(rtex->real_format, height);
- tile_height = r600_get_height_alignment(screen,
- rtex->array_mode[level]);
+ enum pipe_format format = rtex->resource.b.b.format;
- /* XXX Hack around an alignment issue. Less tests fail with this.
- *
- * The thing is depth-stencil buffers should be tiled, i.e.
- * the alignment should be >=8. If I make them tiled, stencil starts
- * working because it no longer overlaps with the depth buffer
- * in memory, but texturing like drawpix-stencil breaks. */
- if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8)
- tile_height = 8;
-
- height = align(height, tile_height);
- return height;
+ return rtex->surface.level[level].offset +
+ box->z * rtex->surface.level[level].slice_size +
+ box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
+ box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
}
-static void r600_texture_set_array_mode(struct pipe_screen *screen,
- struct r600_resource_texture *rtex,
- unsigned level, unsigned array_mode)
+static int r600_init_surface(struct r600_screen *rscreen,
+ struct radeon_surface *surface,
+ const struct pipe_resource *ptex,
+ unsigned array_mode,
+ bool is_flushed_depth)
{
- struct pipe_resource *ptex = &rtex->resource.b.b;
-
- switch (array_mode) {
- case V_009910_ARRAY_LINEAR_GENERAL:
- case V_009910_ARRAY_LINEAR_ALIGNED:
- case V_009910_ARRAY_1D_TILED_THIN1:
- default:
- rtex->array_mode[level] = array_mode;
- break;
- case V_009910_ARRAY_2D_TILED_THIN1:
- {
- unsigned w, h, tile_height, tile_width;
+ const struct util_format_description *desc =
+ util_format_description(ptex->format);
+ bool is_depth, is_stencil;
- tile_height = r600_get_height_alignment(screen, array_mode);
- tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode);
-
- w = mip_minify(ptex->width0, level);
- h = mip_minify(ptex->height0, level);
- if (w <= tile_width || h <= tile_height)
- rtex->array_mode[level] = V_009910_ARRAY_1D_TILED_THIN1;
- else
- rtex->array_mode[level] = array_mode;
- }
- break;
- }
-}
+ is_depth = util_format_has_depth(desc);
+ is_stencil = util_format_has_stencil(desc);
-static int r600_init_surface(struct radeon_surface *surface,
- const struct pipe_resource *ptex,
- unsigned array_mode)
-{
surface->npix_x = ptex->width0;
surface->npix_y = ptex->height0;
surface->npix_z = ptex->depth0;
surface->blk_d = 1;
surface->array_size = 1;
surface->last_level = ptex->last_level;
- surface->bpe = util_format_get_blocksize(ptex->format);
- /* align byte per element on dword */
- if (surface->bpe == 3) {
- surface->bpe = 4;
+
+ if (!is_flushed_depth &&
+ ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
+ surface->bpe = 4; /* stencil is allocated separately on evergreen */
+ } else {
+ surface->bpe = util_format_get_blocksize(ptex->format);
+ /* align byte per element on dword */
+ if (surface->bpe == 3) {
+ surface->bpe = 4;
+ }
}
- surface->nsamples = 1;
+
+ surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
surface->flags = 0;
+
switch (array_mode) {
case V_009910_ARRAY_1D_TILED_THIN1:
surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
if (ptex->bind & PIPE_BIND_SCANOUT) {
surface->flags |= RADEON_SURF_SCANOUT;
}
- if (util_format_is_depth_and_stencil(ptex->format)) {
+
+ if (!is_flushed_depth && is_depth) {
surface->flags |= RADEON_SURF_ZBUFFER;
- surface->flags |= RADEON_SURF_SBUFFER;
+ if (is_stencil) {
+ surface->flags |= RADEON_SURF_SBUFFER |
+ RADEON_SURF_HAS_SBUFFER_MIPTREE;
+ }
}
-
+ surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
return 0;
}
static int r600_setup_surface(struct pipe_screen *screen,
- struct r600_resource_texture *rtex,
- unsigned array_mode,
+ struct r600_texture *rtex,
unsigned pitch_in_bytes_override)
{
- struct pipe_resource *ptex = &rtex->resource.b.b;
struct r600_screen *rscreen = (struct r600_screen*)screen;
- unsigned i;
int r;
- if (util_format_is_depth_or_stencil(rtex->real_format)) {
- rtex->surface.flags |= RADEON_SURF_ZBUFFER;
- rtex->surface.flags |= RADEON_SURF_SBUFFER;
- }
-
r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
if (r) {
return r;
}
+
rtex->size = rtex->surface.bo_size;
+
if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
/* old ddx on evergreen over estimate alignment for 1d, only 1 level
* for those
rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
- rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
- }
- }
- for (i = 0; i <= ptex->last_level; i++) {
- rtex->offset[i] = rtex->surface.level[i].offset;
- rtex->layer_size[i] = rtex->surface.level[i].slice_size;
- rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes;
- switch (rtex->surface.level[i].mode) {
- case RADEON_SURF_MODE_LINEAR_ALIGNED:
- rtex->array_mode[i] = V_009910_ARRAY_LINEAR_ALIGNED;
- break;
- case RADEON_SURF_MODE_1D:
- rtex->array_mode[i] = V_009910_ARRAY_1D_TILED_THIN1;
- break;
- case RADEON_SURF_MODE_2D:
- rtex->array_mode[i] = V_009910_ARRAY_2D_TILED_THIN1;
- break;
- default:
- case RADEON_SURF_MODE_LINEAR:
- rtex->array_mode[i] = 0;
- break;
+ rtex->surface.stencil_offset =
+ rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
}
}
return 0;
}
-static void r600_setup_miptree(struct pipe_screen *screen,
- struct r600_resource_texture *rtex,
- unsigned array_mode)
-{
- struct pipe_resource *ptex = &rtex->resource.b.b;
- enum chip_class chipc = ((struct r600_screen*)screen)->chip_class;
- unsigned size, layer_size, i, offset;
- unsigned nblocksx, nblocksy;
-
- for (i = 0, offset = 0; i <= ptex->last_level; i++) {
- unsigned blocksize = util_format_get_blocksize(rtex->real_format);
- unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode);
-
- r600_texture_set_array_mode(screen, rtex, i, array_mode);
-
- nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
- nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
-
- if (array_mode == V_009910_ARRAY_LINEAR_GENERAL)
- layer_size = align(nblocksx, 64) * nblocksy * blocksize;
- else
- layer_size = nblocksx * nblocksy * blocksize;
-
- if (ptex->target == PIPE_TEXTURE_CUBE) {
- if (chipc >= CAYMAN)
- size = layer_size * 8;
- }
- else if (ptex->target == PIPE_TEXTURE_3D)
- size = layer_size * u_minify(ptex->depth0, i);
- else
- size = layer_size * ptex->array_size;
-
- /* align base image and start of miptree */
- if ((i == 0) || (i == 1))
- offset = align(offset, base_align);
- rtex->offset[i] = offset;
- rtex->layer_size[i] = layer_size;
- rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
- rtex->pitch_in_bytes[i] = nblocksx * blocksize;
-
- offset += size;
- }
- rtex->size = offset;
-}
-
-/* Figure out whether u_blitter will fallback to a transfer operation.
- * If so, don't use a staging resource.
- */
-static boolean permit_hardware_blit(struct pipe_screen *screen,
- const struct pipe_resource *res)
-{
- unsigned bind;
-
- if (util_format_is_depth_or_stencil(res->format))
- bind = PIPE_BIND_DEPTH_STENCIL;
- else
- bind = PIPE_BIND_RENDER_TARGET;
-
- /* hackaround for S3TC */
- if (util_format_is_compressed(res->format))
- return TRUE;
-
- if (!screen->is_format_supported(screen,
- res->format,
- res->target,
- res->nr_samples,
- bind))
- return FALSE;
-
- if (!screen->is_format_supported(screen,
- res->format,
- res->target,
- res->nr_samples,
- PIPE_BIND_SAMPLER_VIEW))
- return FALSE;
-
- switch (res->usage) {
- case PIPE_USAGE_STREAM:
- case PIPE_USAGE_STAGING:
- return FALSE;
-
- default:
- return TRUE;
- }
-}
-
static boolean r600_texture_get_handle(struct pipe_screen* screen,
struct pipe_resource *ptex,
struct winsys_handle *whandle)
{
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
- struct r600_resource *resource = &rtex->resource;
+ struct r600_texture *rtex = (struct r600_texture*)ptex;
+ struct si_resource *resource = &rtex->resource;
struct radeon_surface *surface = &rtex->surface;
struct r600_screen *rscreen = (struct r600_screen*)screen;
rscreen->ws->buffer_set_tiling(resource->buf,
+ NULL,
surface->level[0].mode >= RADEON_SURF_MODE_1D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
surface->level[0].mode >= RADEON_SURF_MODE_2D ?
surface->tile_split,
surface->stencil_tile_split,
surface->mtilea,
- rtex->pitch_in_bytes[0]);
+ surface->level[0].pitch_bytes);
return rscreen->ws->buffer_get_handle(resource->buf,
- rtex->pitch_in_bytes[0], whandle);
+ surface->level[0].pitch_bytes, whandle);
}
static void r600_texture_destroy(struct pipe_screen *screen,
struct pipe_resource *ptex)
{
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
- struct r600_resource *resource = &rtex->resource;
+ struct r600_texture *rtex = (struct r600_texture*)ptex;
+ struct si_resource *resource = &rtex->resource;
if (rtex->flushed_depth_texture)
- pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
-
- if (rtex->stencil)
- pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL);
+ si_resource_reference((struct si_resource **)&rtex->flushed_depth_texture, NULL);
pb_reference(&resource->buf, NULL);
FREE(rtex);
}
-static const struct u_resource_vtbl r600_texture_vtbl =
+static const struct u_resource_vtbl r600_texture_vtbl;
+
+DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth, "RADEON_PRINT_TEXDEPTH", FALSE);
+
+/* The number of samples can be specified independently of the texture. */
+static void r600_texture_get_fmask_info(struct r600_screen *rscreen,
+ struct r600_texture *rtex,
+ unsigned nr_samples,
+ struct r600_fmask_info *out)
{
- r600_texture_get_handle, /* get_handle */
- r600_texture_destroy, /* resource_destroy */
- r600_texture_get_transfer, /* get_transfer */
- r600_texture_transfer_destroy, /* transfer_destroy */
- r600_texture_transfer_map, /* transfer_map */
- u_default_transfer_flush_region,/* transfer_flush_region */
- r600_texture_transfer_unmap, /* transfer_unmap */
- NULL /* transfer_inline_write */
-};
+ /* FMASK is allocated like an ordinary texture. */
+ struct radeon_surface fmask = rtex->surface;
+
+ memset(out, 0, sizeof(*out));
+
+ fmask.bo_alignment = 0;
+ fmask.bo_size = 0;
+ fmask.nsamples = 1;
+ fmask.flags |= RADEON_SURF_FMASK | RADEON_SURF_HAS_TILE_MODE_INDEX;
-static struct r600_resource_texture *
+ switch (nr_samples) {
+ case 2:
+ case 4:
+ fmask.bpe = 1;
+ break;
+ case 8:
+ fmask.bpe = 4;
+ break;
+ default:
+ R600_ERR("Invalid sample count for FMASK allocation.\n");
+ return;
+ }
+
+ if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
+ R600_ERR("Got error in surface_init while allocating FMASK.\n");
+ return;
+ }
+
+ assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
+
+ out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
+ if (out->slice_tile_max)
+ out->slice_tile_max -= 1;
+
+ out->tile_mode_index = fmask.tiling_index[0];
+ out->pitch = fmask.level[0].nblk_x;
+ out->bank_height = fmask.bankh;
+ out->alignment = MAX2(256, fmask.bo_alignment);
+ out->size = fmask.bo_size;
+}
+
+static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
+ struct r600_texture *rtex)
+{
+ r600_texture_get_fmask_info(rscreen, rtex,
+ rtex->resource.b.b.nr_samples, &rtex->fmask);
+
+ rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
+ rtex->size = rtex->fmask.offset + rtex->fmask.size;
+}
+
+static void si_texture_get_cmask_info(struct r600_screen *rscreen,
+ struct r600_texture *rtex,
+ struct r600_cmask_info *out)
+{
+ unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
+ unsigned num_pipes = rscreen->tiling_info.num_channels;
+ unsigned cl_width, cl_height;
+
+ switch (num_pipes) {
+ case 2:
+ cl_width = 32;
+ cl_height = 16;
+ break;
+ case 4:
+ cl_width = 32;
+ cl_height = 32;
+ break;
+ case 8:
+ cl_width = 64;
+ cl_height = 32;
+ break;
+ default:
+ assert(0);
+ return;
+ }
+
+ unsigned base_align = num_pipes * pipe_interleave_bytes;
+
+ unsigned width = align(rtex->surface.npix_x, cl_width*8);
+ unsigned height = align(rtex->surface.npix_y, cl_height*8);
+ unsigned slice_elements = (width * height) / (8*8);
+
+ /* Each element of CMASK is a nibble. */
+ unsigned slice_bytes = slice_elements / 2;
+
+ out->slice_tile_max = (width * height) / (128*128);
+ if (out->slice_tile_max)
+ out->slice_tile_max -= 1;
+
+ out->alignment = MAX2(256, base_align);
+ out->size = rtex->surface.array_size * align(slice_bytes, base_align);
+}
+
+static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
+ struct r600_texture *rtex)
+{
+ si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
+
+ if (rtex->cmask.size) {
+ rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
+ rtex->size = rtex->cmask.offset + rtex->cmask.size;
+ }
+}
+
+static struct r600_texture *
r600_texture_create_object(struct pipe_screen *screen,
const struct pipe_resource *base,
- unsigned array_mode,
unsigned pitch_in_bytes_override,
- unsigned max_buffer_size,
struct pb_buffer *buf,
- boolean alloc_bo,
struct radeon_surface *surface)
{
- struct r600_resource_texture *rtex;
- struct r600_resource *resource;
+ struct r600_texture *rtex;
+ struct si_resource *resource;
struct r600_screen *rscreen = (struct r600_screen*)screen;
int r;
- rtex = CALLOC_STRUCT(r600_resource_texture);
+ rtex = CALLOC_STRUCT(r600_texture);
if (rtex == NULL)
return NULL;
pipe_reference_init(&resource->b.b.reference, 1);
resource->b.b.screen = screen;
rtex->pitch_override = pitch_in_bytes_override;
- rtex->real_format = base->format;
- /* only mark depth textures the HW can hit as depth textures */
- if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
- rtex->depth = 1;
+ /* don't include stencil-only formats which we don't support for rendering */
+ rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
- r600_setup_miptree(screen, rtex, array_mode);
rtex->surface = *surface;
- r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
+ r = r600_setup_surface(screen, rtex, pitch_in_bytes_override);
if (r) {
FREE(rtex);
return NULL;
}
- /* If we initialized separate stencil for Evergreen. place it after depth. */
- if (rtex->stencil) {
- unsigned stencil_align, stencil_offset;
-
- stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode);
- stencil_offset = align(rtex->size, stencil_align);
-
- for (unsigned i = 0; i <= rtex->stencil->resource.b.b.last_level; i++)
- rtex->stencil->offset[i] += stencil_offset;
+ if (base->nr_samples > 1 && !rtex->is_depth && !buf) {
+ r600_texture_allocate_fmask(rscreen, rtex);
+ r600_texture_allocate_cmask(rscreen, rtex);
+ }
- rtex->size = stencil_offset + rtex->stencil->size;
+ if (!rtex->is_depth && base->nr_samples > 1 &&
+ (!rtex->fmask.size || !rtex->cmask.size)) {
+ FREE(rtex);
+ return NULL;
}
/* Now create the backing buffer. */
- if (!buf && alloc_bo) {
- struct pipe_resource *ptex = &rtex->resource.b.b;
- unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
+ if (!buf) {
+ unsigned base_align = rtex->surface.bo_alignment;
- base_align = rtex->surface.bo_alignment;
- if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
- pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL);
+ if (!si_init_resource(rscreen, resource, rtex->size, base_align, FALSE, base->usage)) {
FREE(rtex);
return NULL;
}
resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
}
- if (rtex->stencil) {
- pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf);
- rtex->stencil->resource.cs_buf = rtex->resource.cs_buf;
- rtex->stencil->resource.domains = rtex->resource.domains;
+ if (rtex->cmask.size) {
+ /* Initialize the cmask to 0xCC (= compressed state). */
+ char *map = rscreen->ws->buffer_map(resource->cs_buf, NULL, PIPE_TRANSFER_WRITE);
+ memset(map + rtex->cmask.offset, 0xCC, rtex->cmask.size);
+ }
+
+ if (debug_get_option_print_texdepth() && rtex->is_depth) {
+ printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
+ "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
+ "bpe=%u, nsamples=%u, flags=%u\n",
+ rtex->surface.npix_x, rtex->surface.npix_y,
+ rtex->surface.npix_z, rtex->surface.blk_w,
+ rtex->surface.blk_h, rtex->surface.blk_d,
+ rtex->surface.array_size, rtex->surface.last_level,
+ rtex->surface.bpe, rtex->surface.nsamples,
+ rtex->surface.flags);
+ if (rtex->surface.flags & RADEON_SURF_ZBUFFER) {
+ for (int i = 0; i <= rtex->surface.last_level; i++) {
+ printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
+ "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
+ "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
+ i, rtex->surface.level[i].offset,
+ rtex->surface.level[i].slice_size,
+ rtex->surface.level[i].npix_x,
+ rtex->surface.level[i].npix_y,
+ rtex->surface.level[i].npix_z,
+ rtex->surface.level[i].nblk_x,
+ rtex->surface.level[i].nblk_y,
+ rtex->surface.level[i].nblk_z,
+ rtex->surface.level[i].pitch_bytes,
+ rtex->surface.level[i].mode);
+ }
+ }
+ if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+ for (int i = 0; i <= rtex->surface.last_level; i++) {
+ printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
+ "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
+ "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
+ i, rtex->surface.stencil_level[i].offset,
+ rtex->surface.stencil_level[i].slice_size,
+ rtex->surface.stencil_level[i].npix_x,
+ rtex->surface.stencil_level[i].npix_y,
+ rtex->surface.stencil_level[i].npix_z,
+ rtex->surface.stencil_level[i].nblk_x,
+ rtex->surface.stencil_level[i].nblk_y,
+ rtex->surface.stencil_level[i].nblk_z,
+ rtex->surface.stencil_level[i].pitch_bytes,
+ rtex->surface.stencil_level[i].mode);
+ }
+ }
}
return rtex;
}
-struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
- const struct pipe_resource *templ)
+struct pipe_resource *si_texture_create(struct pipe_screen *screen,
+ const struct pipe_resource *templ)
{
struct r600_screen *rscreen = (struct r600_screen*)screen;
- struct radeon_surface surface;
- unsigned array_mode = 0;
+ struct radeon_surface surface = {0};
+ unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
int r;
if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
- !(templ->bind & PIPE_BIND_SCANOUT)) {
- if (permit_hardware_blit(screen, templ)) {
+ !(templ->bind & PIPE_BIND_CURSOR)) {
+ if (templ->flags & R600_RESOURCE_FLAG_FORCE_TILING ||
+ templ->nr_samples > 1) {
array_mode = V_009910_ARRAY_2D_TILED_THIN1;
+ } else if (util_format_is_compressed(templ->format)) {
+ array_mode = V_009910_ARRAY_1D_TILED_THIN1;
+ } else if (templ->usage != PIPE_USAGE_STAGING &&
+ templ->usage != PIPE_USAGE_STREAM &&
+ templ->target != PIPE_TEXTURE_1D &&
+ templ->target != PIPE_TEXTURE_1D_ARRAY &&
+ templ->height0 > 3 &&
+ rscreen->chip_class < CIK /* XXX fix me */) {
+ array_mode = V_009910_ARRAY_2D_TILED_THIN1;
+ } else {
+ array_mode = V_009910_ARRAY_1D_TILED_THIN1;
}
}
- r = r600_init_surface(&surface, templ, array_mode);
+ r = r600_init_surface(rscreen, &surface, templ, array_mode,
+ templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
if (r) {
return NULL;
}
if (r) {
return NULL;
}
- return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
- 0, 0, NULL, TRUE, &surface);
+ return (struct pipe_resource *)r600_texture_create_object(screen, templ,
+ 0, NULL, &surface);
}
static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
struct pipe_resource *texture,
const struct pipe_surface *surf_tmpl)
{
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
+ struct r600_texture *rtex = (struct r600_texture*)texture;
struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
unsigned level = surf_tmpl->u.tex.level;
+ assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
+ assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
if (surface == NULL)
return NULL;
pipe_resource_reference(&surface->base.texture, texture);
surface->base.context = pipe;
surface->base.format = surf_tmpl->format;
- surface->base.width = mip_minify(texture->width0, level);
- surface->base.height = mip_minify(texture->height0, level);
- surface->base.usage = surf_tmpl->usage;
+ surface->base.width = rtex->surface.level[level].npix_x;
+ surface->base.height = rtex->surface.level[level].npix_y;
surface->base.texture = texture;
surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
surface->base.u.tex.level = level;
- surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
- rtex, level);
return &surface->base;
}
FREE(surface);
}
-struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
- const struct pipe_resource *templ,
- struct winsys_handle *whandle)
+struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
+ const struct pipe_resource *templ,
+ struct winsys_handle *whandle)
{
struct r600_screen *rscreen = (struct r600_screen*)screen;
struct pb_buffer *buf = NULL;
unsigned stride = 0;
- unsigned array_mode = 0;
+ unsigned array_mode;
enum radeon_bo_layout micro, macro;
struct radeon_surface surface;
int r;
else if (micro == RADEON_LAYOUT_TILED)
array_mode = V_009910_ARRAY_1D_TILED_THIN1;
else
- array_mode = 0;
+ array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
- r = r600_init_surface(&surface, templ, array_mode);
+ r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
if (r) {
return NULL;
}
- return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
- stride, 0, buf, FALSE, &surface);
+
+ /* always set the scanout flags */
+ surface.flags |= RADEON_SURF_SCANOUT;
+
+ return (struct pipe_resource *)r600_texture_create_object(screen, templ,
+ stride, buf, &surface);
}
-int r600_texture_depth_flush(struct pipe_context *ctx,
- struct pipe_resource *texture, boolean just_create)
+bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
+ struct pipe_resource *texture,
+ struct r600_texture **staging)
{
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
+ struct r600_texture *rtex = (struct r600_texture*)texture;
struct pipe_resource resource;
+ struct r600_texture **flushed_depth_texture = staging ?
+ staging : &rtex->flushed_depth_texture;
- if (rtex->flushed_depth_texture)
- goto out;
+ if (!staging && rtex->flushed_depth_texture)
+ return true; /* it's ready */
resource.target = texture->target;
resource.format = texture->format;
resource.array_size = texture->array_size;
resource.last_level = texture->last_level;
resource.nr_samples = texture->nr_samples;
- resource.usage = PIPE_USAGE_DYNAMIC;
- resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL;
- resource.flags = R600_RESOURCE_FLAG_TRANSFER | texture->flags;
+ resource.usage = staging ? PIPE_USAGE_DYNAMIC : PIPE_USAGE_DEFAULT;
+ resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
+ resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
- rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
- if (rtex->flushed_depth_texture == NULL) {
- R600_ERR("failed to create temporary texture to hold untiled copy\n");
- return -ENOMEM;
- }
+ if (staging)
+ resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
- ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
-out:
- if (just_create)
- return 0;
+ *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
+ if (*flushed_depth_texture == NULL) {
+ R600_ERR("failed to create temporary texture to hold flushed depth\n");
+ return false;
+ }
- /* XXX: only do this if the depth texture has actually changed:
- */
- r600_blit_uncompress_depth(ctx, rtex);
- return 0;
+ (*flushed_depth_texture)->is_flushing_texture = TRUE;
+ return true;
}
-/* Needs adjustment for pixelformat:
+/**
+ * Initialize the pipe_resource descriptor to be of the same size as the box,
+ * which is supposed to hold a subregion of the texture "orig" at the given
+ * mipmap level.
*/
-static INLINE unsigned u_box_volume( const struct pipe_box *box )
+static void r600_init_temp_resource_from_box(struct pipe_resource *res,
+ struct pipe_resource *orig,
+ const struct pipe_box *box,
+ unsigned level, unsigned flags)
{
- return box->width * box->depth * box->height;
-};
+ memset(res, 0, sizeof(*res));
+ res->format = orig->format;
+ res->width0 = box->width;
+ res->height0 = box->height;
+ res->depth0 = 1;
+ res->array_size = 1;
+ res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
+ res->flags = flags;
+
+ /* We must set the correct texture target and dimensions for a 3D box. */
+ if (box->depth > 1 && util_max_layer(orig, level) > 0)
+ res->target = orig->target;
+ else
+ res->target = PIPE_TEXTURE_2D;
-struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
- struct pipe_resource *texture,
- unsigned level,
- unsigned usage,
- const struct pipe_box *box)
+ switch (res->target) {
+ case PIPE_TEXTURE_1D_ARRAY:
+ case PIPE_TEXTURE_2D_ARRAY:
+ case PIPE_TEXTURE_CUBE_ARRAY:
+ res->array_size = box->depth;
+ break;
+ case PIPE_TEXTURE_3D:
+ res->depth0 = box->depth;
+ break;
+ default:;
+ }
+}
+
+static void *si_texture_transfer_map(struct pipe_context *ctx,
+ struct pipe_resource *texture,
+ unsigned level,
+ unsigned usage,
+ const struct pipe_box *box,
+ struct pipe_transfer **ptransfer)
{
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
- struct pipe_resource resource;
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_texture *rtex = (struct r600_texture*)texture;
struct r600_transfer *trans;
- int r;
boolean use_staging_texture = FALSE;
+ struct radeon_winsys_cs_handle *buf;
+ unsigned offset = 0;
+ char *map;
/* We cannot map a tiled texture directly because the data is
* in a different order, therefore we do detiling using a blit.
* the CPU is much happier reading out of cached system memory
* than uncached VRAM.
*/
- if (R600_TEX_IS_TILED(rtex, level))
- use_staging_texture = TRUE;
-
- if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
+ if (rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR_ALIGNED &&
+ rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR)
use_staging_texture = TRUE;
- /* XXX: Use a staging texture for uploads if the underlying BO
- * is busy. No interface for checking that currently? so do
- * it eagerly whenever the transfer doesn't require a readback
- * and might block.
- */
- if ((usage & PIPE_TRANSFER_WRITE) &&
- !(usage & (PIPE_TRANSFER_READ |
- PIPE_TRANSFER_DONTBLOCK |
- PIPE_TRANSFER_UNSYNCHRONIZED)))
+ /* Use a staging texture for uploads if the underlying BO is busy. */
+ if (!(usage & PIPE_TRANSFER_READ) &&
+ (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
+ rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
use_staging_texture = TRUE;
+ }
- if (!permit_hardware_blit(ctx->screen, texture) ||
- (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
+ if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
use_staging_texture = FALSE;
+ }
- if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY))
+ if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
return NULL;
+ }
trans = CALLOC_STRUCT(r600_transfer);
if (trans == NULL)
return NULL;
- pipe_resource_reference(&trans->transfer.resource, texture);
+ trans->transfer.resource = texture;
trans->transfer.level = level;
trans->transfer.usage = usage;
trans->transfer.box = *box;
- if (rtex->depth) {
- /* XXX: only readback the rectangle which is being mapped?
- */
- /* XXX: when discard is true, no need to read back from depth texture
- */
- r = r600_texture_depth_flush(ctx, texture, FALSE);
- if (r < 0) {
- R600_ERR("failed to create temporary texture to hold untiled copy\n");
- pipe_resource_reference(&trans->transfer.resource, NULL);
- FREE(trans);
- return NULL;
- }
- trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
- trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
- return &trans->transfer;
- } else if (use_staging_texture) {
- resource.target = PIPE_TEXTURE_2D;
- resource.format = texture->format;
- resource.width0 = box->width;
- resource.height0 = box->height;
- resource.depth0 = 1;
- resource.array_size = 1;
- resource.last_level = 0;
- resource.nr_samples = 0;
- resource.usage = PIPE_USAGE_STAGING;
- resource.bind = 0;
- resource.flags = R600_RESOURCE_FLAG_TRANSFER;
- /* For texture reading, the temporary (detiled) texture is used as
- * a render target when blitting from a tiled texture. */
- if (usage & PIPE_TRANSFER_READ) {
- resource.bind |= PIPE_BIND_RENDER_TARGET;
+
+ if (rtex->is_depth) {
+ struct r600_texture *staging_depth;
+
+ if (rtex->resource.b.b.nr_samples > 1) {
+ /* MSAA depth buffers need to be converted to single sample buffers.
+ *
+ * Mapping MSAA depth buffers can occur if ReadPixels is called
+ * with a multisample GLX visual.
+ *
+ * First downsample the depth buffer to a temporary texture,
+ * then decompress the temporary one to staging.
+ *
+ * Only the region being mapped is transfered.
+ */
+ struct pipe_resource resource;
+
+ r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
+
+ if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
+ R600_ERR("failed to create temporary texture to hold untiled copy\n");
+ FREE(trans);
+ return NULL;
+ }
+
+ if (usage & PIPE_TRANSFER_READ) {
+ struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
+
+ r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
+ r600_blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
+ 0, 0, 0, box->depth, 0, 0);
+ pipe_resource_reference((struct pipe_resource**)&temp, NULL);
+ }
}
- /* For texture writing, the temporary texture is used as a sampler
- * when blitting into a tiled texture. */
- if (usage & PIPE_TRANSFER_WRITE) {
- resource.bind |= PIPE_BIND_SAMPLER_VIEW;
+ else {
+ /* XXX: only readback the rectangle which is being mapped? */
+ /* XXX: when discard is true, no need to read back from depth texture */
+ if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
+ R600_ERR("failed to create temporary texture to hold untiled copy\n");
+ FREE(trans);
+ return NULL;
+ }
+
+ r600_blit_decompress_depth(ctx, rtex, staging_depth,
+ level, level,
+ box->z, box->z + box->depth - 1,
+ 0, 0);
+
+ offset = r600_texture_get_offset(staging_depth, level, box);
}
+
+ trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
+ trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
+ trans->staging = (struct si_resource*)staging_depth;
+ } else if (use_staging_texture) {
+ struct pipe_resource resource;
+ struct r600_texture *staging;
+
+ r600_init_temp_resource_from_box(&resource, texture, box, level,
+ R600_RESOURCE_FLAG_TRANSFER);
+
/* Create the temporary texture. */
- trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
- if (trans->staging_texture == NULL) {
+ staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
+ if (staging == NULL) {
R600_ERR("failed to create temporary texture to hold untiled copy\n");
- pipe_resource_reference(&trans->transfer.resource, NULL);
FREE(trans);
return NULL;
}
-
- trans->transfer.stride =
- ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
+ trans->staging = &staging->resource;
+ trans->transfer.stride = staging->surface.level[0].pitch_bytes;
+ trans->transfer.layer_stride = staging->surface.level[0].slice_size;
if (usage & PIPE_TRANSFER_READ) {
r600_copy_to_staging_texture(ctx, trans);
- /* Always referenced in the blit. */
- radeonsi_flush(ctx, NULL, 0);
- }
- return &trans->transfer;
- }
- trans->transfer.stride = rtex->pitch_in_bytes[level];
- trans->transfer.layer_stride = rtex->layer_size[level];
- trans->offset = r600_texture_get_offset(rtex, level, box->z);
- return &trans->transfer;
-}
-
-void r600_texture_transfer_destroy(struct pipe_context *ctx,
- struct pipe_transfer *transfer)
-{
- struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
- struct pipe_resource *texture = transfer->resource;
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
-
- if (rtransfer->staging_texture) {
- if (transfer->usage & PIPE_TRANSFER_WRITE) {
- r600_copy_from_staging_texture(ctx, rtransfer);
}
- pipe_resource_reference(&rtransfer->staging_texture, NULL);
- }
-
- if (rtex->depth && !rtex->is_flushing_texture) {
- if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
- r600_blit_push_depth(ctx, rtex);
+ } else {
+ /* the resource is mapped directly */
+ trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
+ trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
+ offset = r600_texture_get_offset(rtex, level, box);
}
- pipe_resource_reference(&transfer->resource, NULL);
- FREE(transfer);
-}
-
-void* r600_texture_transfer_map(struct pipe_context *ctx,
- struct pipe_transfer* transfer)
-{
- struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
- struct radeon_winsys_cs_handle *buf;
- enum pipe_format format = transfer->resource->format;
- unsigned offset = 0;
- char *map;
-
- if (rtransfer->staging_texture) {
- buf = ((struct r600_resource *)rtransfer->staging_texture)->cs_buf;
+ if (trans->staging) {
+ buf = trans->staging->cs_buf;
} else {
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
-
- if (rtex->flushed_depth_texture)
- buf = ((struct r600_resource *)rtex->flushed_depth_texture)->cs_buf;
- else
- buf = ((struct r600_resource *)transfer->resource)->cs_buf;
-
- offset = rtransfer->offset +
- transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
- transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
+ buf = rtex->resource.cs_buf;
}
- if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) {
+ if (!(map = rctx->ws->buffer_map(buf, rctx->cs, usage))) {
+ pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
+ FREE(trans);
return NULL;
}
+ *ptransfer = &trans->transfer;
return map + offset;
}
-void r600_texture_transfer_unmap(struct pipe_context *ctx,
- struct pipe_transfer* transfer)
+static void si_texture_transfer_unmap(struct pipe_context *ctx,
+ struct pipe_transfer* transfer)
{
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
struct r600_context *rctx = (struct r600_context*)ctx;
struct radeon_winsys_cs_handle *buf;
+ struct pipe_resource *texture = transfer->resource;
+ struct r600_texture *rtex = (struct r600_texture*)texture;
- if (rtransfer->staging_texture) {
- buf = ((struct r600_resource *)rtransfer->staging_texture)->cs_buf;
+ if (rtransfer->staging) {
+ buf = rtransfer->staging->cs_buf;
} else {
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
+ buf = si_resource(transfer->resource)->cs_buf;
+ }
+ rctx->ws->buffer_unmap(buf);
- if (rtex->flushed_depth_texture) {
- buf = ((struct r600_resource *)rtex->flushed_depth_texture)->cs_buf;
+ if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
+ if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
+ ctx->resource_copy_region(ctx, texture, transfer->level,
+ transfer->box.x, transfer->box.y, transfer->box.z,
+ &rtransfer->staging->b.b, transfer->level,
+ &transfer->box);
} else {
- buf = ((struct r600_resource *)transfer->resource)->cs_buf;
+ r600_copy_from_staging_texture(ctx, rtransfer);
}
}
- rctx->ws->buffer_unmap(buf);
+
+ if (rtransfer->staging)
+ pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
+
+ FREE(transfer);
}
-void r600_init_surface_functions(struct r600_context *r600)
+void si_init_surface_functions(struct r600_context *r600)
{
r600->context.create_surface = r600_create_surface;
r600->context.surface_destroy = r600_surface_destroy;
}
+
+static const struct u_resource_vtbl r600_texture_vtbl =
+{
+ r600_texture_get_handle, /* get_handle */
+ r600_texture_destroy, /* resource_destroy */
+ si_texture_transfer_map, /* transfer_map */
+ u_default_transfer_flush_region,/* transfer_flush_region */
+ si_texture_transfer_unmap, /* transfer_unmap */
+ NULL /* transfer_inline_write */
+};
projects / mesa.git / blobdiff