#include "util/u_pack_color.h"
#include "util/u_memory.h"
#include "util/u_inlines.h"
+#include "util/u_simple_shaders.h"
#include "util/u_upload_mgr.h"
#include "vl/vl_decoder.h"
#include "vl/vl_video_buffer.h"
#include "os/os_time.h"
#include "pipebuffer/pb_buffer.h"
+#include "radeonsi_pipe.h"
+#include "radeon/radeon_uvd.h"
#include "r600.h"
#include "sid.h"
#include "r600_resource.h"
if (!rscreen->fences.bo) {
/* Create the shared buffer object */
- rscreen->fences.bo = (struct r600_resource*)
- pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
- PIPE_USAGE_STAGING, 4096);
+ rscreen->fences.bo = si_resource_create_custom(&rscreen->screen,
+ PIPE_USAGE_STAGING,
+ 4096);
if (!rscreen->fences.bo) {
R600_ERR("r600: failed to create bo for fence objects\n");
goto out;
pipe_reference_init(&fence->reference, 1);
rscreen->fences.data[fence->index] = 0;
- r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
+ si_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
/* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
- fence->sleep_bo = (struct r600_resource*)
- pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
- PIPE_USAGE_STAGING, 1);
+ fence->sleep_bo = si_resource_create_custom(&rctx->screen->screen, PIPE_USAGE_STAGING, 1);
+
/* Add the fence as a dummy relocation. */
r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
ctx->render_condition(ctx, NULL, 0);
}
- r600_context_flush(rctx, flags);
+ si_context_flush(rctx, flags);
/* Re-enable render condition. */
if (render_cond) {
}
static void r600_flush_from_st(struct pipe_context *ctx,
- struct pipe_fence_handle **fence)
+ struct pipe_fence_handle **fence,
+ unsigned flags)
{
- radeonsi_flush(ctx, fence, 0);
+ radeonsi_flush(ctx, fence,
+ flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
}
static void r600_flush_from_winsys(void *ctx, unsigned flags)
{
struct r600_context *rctx = (struct r600_context *)context;
- rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
- util_unreference_framebuffer_state(&rctx->framebuffer);
+ si_resource_reference(&rctx->border_color_table, NULL);
- r600_context_fini(rctx);
+ if (rctx->dummy_pixel_shader) {
+ rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
+ }
+ rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_depth_stencil);
+ rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_depth);
+ rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_stencil);
+ rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_inplace);
+ util_unreference_framebuffer_state(&rctx->framebuffer);
util_blitter_destroy(rctx->blitter);
- for (int i = 0; i < R600_PIPE_NSTATES; i++) {
- free(rctx->states[i]);
- }
-
if (rctx->uploader) {
u_upload_destroy(rctx->uploader);
}
rctx->family = rscreen->family;
rctx->chip_class = rscreen->chip_class;
- r600_init_blit_functions(rctx);
+ si_init_blit_functions(rctx);
r600_init_query_functions(rctx);
r600_init_context_resource_functions(rctx);
- r600_init_surface_functions(rctx);
- rctx->context.draw_vbo = r600_draw_vbo;
+ si_init_surface_functions(rctx);
+ si_init_compute_functions(rctx);
- rctx->context.create_video_decoder = vl_create_decoder;
- rctx->context.create_video_buffer = vl_video_buffer_create;
-
- r600_init_common_atoms(rctx);
+ if (rscreen->info.has_uvd) {
+ rctx->context.create_video_decoder = radeonsi_uvd_create_decoder;
+ rctx->context.create_video_buffer = radeonsi_video_buffer_create;
+ } else {
+ rctx->context.create_video_decoder = vl_create_decoder;
+ rctx->context.create_video_buffer = vl_video_buffer_create;
+ }
switch (rctx->chip_class) {
case TAHITI:
- cayman_init_state_functions(rctx);
- if (si_context_init(rctx)) {
- r600_destroy_context(&rctx->context);
- return NULL;
- }
+ si_init_state_functions(rctx);
+ LIST_INITHEAD(&rctx->active_query_list);
+ rctx->cs = rctx->ws->cs_create(rctx->ws, RING_GFX, NULL);
+ rctx->max_db = 8;
si_init_config(rctx);
break;
default:
return NULL;
}
- LIST_INITHEAD(&rctx->dirty_states);
+ si_get_backend_mask(rctx); /* this emits commands and must be last */
- r600_get_backend_mask(rctx); /* this emits commands and must be last */
+ rctx->dummy_pixel_shader =
+ util_make_fragment_cloneinput_shader(&rctx->context, 0,
+ TGSI_SEMANTIC_GENERIC,
+ TGSI_INTERPOLATE_CONSTANT);
+ rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
return &rctx->context;
}
return "X.Org";
}
+const char *r600_get_llvm_processor_name(enum radeon_family family)
+{
+ switch (family) {
+ case CHIP_TAHITI: return "tahiti";
+ case CHIP_PITCAIRN: return "pitcairn";
+ case CHIP_VERDE: return "verde";
+ case CHIP_OLAND: return "oland";
+ default: return "";
+ }
+}
+
static const char *r600_get_family_name(enum radeon_family family)
{
switch(family) {
case CHIP_TAHITI: return "AMD TAHITI";
case CHIP_PITCAIRN: return "AMD PITCAIRN";
case CHIP_VERDE: return "AMD CAPE VERDE";
+ case CHIP_OLAND: return "AMD OLAND";
default: return "AMD unknown";
}
}
static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
{
struct r600_screen *rscreen = (struct r600_screen *)pscreen;
- enum radeon_family family = rscreen->family;
switch (param) {
/* Supported features (boolean caps). */
- case PIPE_CAP_NPOT_TEXTURES:
case PIPE_CAP_TWO_SIDED_STENCIL:
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
case PIPE_CAP_ANISOTROPIC_FILTER:
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_TEXTURE_SWIZZLE:
- case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_SHADER_STENCIL_EXPORT:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
case PIPE_CAP_USER_INDEX_BUFFERS:
case PIPE_CAP_USER_CONSTANT_BUFFERS:
case PIPE_CAP_START_INSTANCE:
+ case PIPE_CAP_NPOT_TEXTURES:
+ case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
+ case PIPE_CAP_TGSI_INSTANCEID:
+ case PIPE_CAP_COMPUTE:
return 1;
+ case PIPE_CAP_TGSI_TEXCOORD:
+ return 0;
+
+ case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
+ return 64;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 256;
return debug_get_bool_option("R600_GLSL130", FALSE) ? 130 : 120;
/* Unsupported features. */
- case PIPE_CAP_TGSI_INSTANCEID:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
case PIPE_CAP_SCALED_RESOLVE:
case PIPE_CAP_VERTEX_COLOR_CLAMPED:
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
case PIPE_CAP_USER_VERTEX_BUFFERS:
+ case PIPE_CAP_TEXTURE_MULTISAMPLE:
+ case PIPE_CAP_QUERY_TIMESTAMP:
+ case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
+ case PIPE_CAP_CUBE_MAP_ARRAY:
+ case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
+ case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
+ case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
return 0;
/* Stream output. */
+#if 0
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0;
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
return 16*4;
+#endif
+ case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
+ case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
+ case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
+ case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
+ return 0;
/* Texturing. */
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
return 15;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
- return rscreen->info.drm_minor >= 9 ? 16384 : 0;
+ return 16384;
case PIPE_CAP_MAX_COMBINED_SAMPLERS:
return 32;
return 8;
/* Timer queries, present when the clock frequency is non zero. */
- case PIPE_CAP_TIMER_QUERY:
+ case PIPE_CAP_QUERY_TIME_ELAPSED:
return rscreen->info.r600_clock_crystal_freq != 0;
case PIPE_CAP_MIN_TEXEL_OFFSET:
static float r600_get_paramf(struct pipe_screen* pscreen,
enum pipe_capf param)
{
- struct r600_screen *rscreen = (struct r600_screen *)pscreen;
- enum radeon_family family = rscreen->family;
-
switch (param) {
case PIPE_CAPF_MAX_LINE_WIDTH:
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
{
- struct r600_screen *rscreen = (struct r600_screen *)pscreen;
switch(shader)
{
case PIPE_SHADER_FRAGMENT:
case PIPE_SHADER_GEOMETRY:
/* TODO: support and enable geometry programs */
return 0;
+ case PIPE_SHADER_COMPUTE:
+ switch (param) {
+ case PIPE_SHADER_CAP_PREFERRED_IR:
+ return PIPE_SHADER_IR_LLVM;
+ default:
+ return 0;
+ }
default:
/* TODO: support tessellation */
return 0;
}
- /* TODO: all these should be fixed, since r600 surely supports much more! */
switch (param) {
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
return 16384;
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
- return 8; /* FIXME */
+ return 32;
case PIPE_SHADER_CAP_MAX_INPUTS:
- if(shader == PIPE_SHADER_FRAGMENT)
- return 34;
- else
- return 32;
+ return 32;
case PIPE_SHADER_CAP_MAX_TEMPS:
return 256; /* Max native temporaries. */
case PIPE_SHADER_CAP_MAX_ADDRS:
/* FIXME Isn't this equal to TEMPS? */
return 1; /* Max native address registers */
case PIPE_SHADER_CAP_MAX_CONSTS:
- return R600_MAX_CONST_BUFFER_SIZE;
+ return 4096; /* actually only memory limits this */
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
- return R600_MAX_CONST_BUFFERS;
+ return 1;
case PIPE_SHADER_CAP_MAX_PREDS:
return 0; /* FIXME */
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 1;
+ case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
+ return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
+ return 1;
case PIPE_SHADER_CAP_INTEGERS:
- return 0;
+ return 1;
case PIPE_SHADER_CAP_SUBROUTINES:
return 0;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
return 16;
+ case PIPE_SHADER_CAP_PREFERRED_IR:
+ return PIPE_SHADER_IR_TGSI;
}
return 0;
}
}
}
+static int r600_get_compute_param(struct pipe_screen *screen,
+ enum pipe_compute_cap param,
+ void *ret)
+{
+ struct r600_screen *rscreen = (struct r600_screen *)screen;
+ //TODO: select these params by asic
+ switch (param) {
+ case PIPE_COMPUTE_CAP_IR_TARGET: {
+ const char *gpu = r600_get_llvm_processor_name(rscreen->family);
+ if (ret) {
+ sprintf(ret, "%s-r600--", gpu);
+ }
+ return (8 + strlen(gpu)) * sizeof(char);
+ }
+ case PIPE_COMPUTE_CAP_GRID_DIMENSION:
+ if (ret) {
+ uint64_t * grid_dimension = ret;
+ grid_dimension[0] = 3;
+ }
+ return 1 * sizeof(uint64_t);
+ case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
+ if (ret) {
+ uint64_t * grid_size = ret;
+ grid_size[0] = 65535;
+ grid_size[1] = 65535;
+ grid_size[2] = 1;
+ }
+ return 3 * sizeof(uint64_t) ;
+
+ case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
+ if (ret) {
+ uint64_t * block_size = ret;
+ block_size[0] = 256;
+ block_size[1] = 256;
+ block_size[2] = 256;
+ }
+ return 3 * sizeof(uint64_t);
+ case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
+ if (ret) {
+ uint64_t * max_threads_per_block = ret;
+ *max_threads_per_block = 256;
+ }
+ return sizeof(uint64_t);
+
+ default:
+ fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
+ return 0;
+ }
+}
+
static void r600_destroy_screen(struct pipe_screen* pscreen)
{
struct r600_screen *rscreen = (struct r600_screen *)pscreen;
}
rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
- pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
+ si_resource_reference(&rscreen->fences.bo, NULL);
}
+
+#if R600_TRACE_CS
+ if (rscreen->trace_bo) {
+ rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
+ pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
+ }
+#endif
+
pipe_mutex_destroy(rscreen->fences.mutex);
rscreen->ws->destroy(rscreen->ws);
if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
struct r600_screen *rscreen = (struct r600_screen *)pscreen;
pipe_mutex_lock(rscreen->fences.mutex);
- pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
+ si_resource_reference(&(*oldf)->sleep_bo, NULL);
LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
pipe_mutex_unlock(rscreen->fences.mutex);
}
struct r600_screen *rscreen = (struct r600_screen *)pscreen;
struct r600_fence *rfence = (struct r600_fence*)fence;
- return rscreen->fences.data[rfence->index];
+ return rscreen->fences.data[rfence->index] != 0;
}
static boolean r600_fence_finish(struct pipe_screen *pscreen,
rscreen->screen.get_param = r600_get_param;
rscreen->screen.get_shader_param = r600_get_shader_param;
rscreen->screen.get_paramf = r600_get_paramf;
- rscreen->screen.get_video_param = r600_get_video_param;
+ rscreen->screen.get_compute_param = r600_get_compute_param;
rscreen->screen.is_format_supported = si_is_format_supported;
- rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
rscreen->screen.context_create = r600_create_context;
rscreen->screen.fence_reference = r600_fence_reference;
rscreen->screen.fence_signalled = r600_fence_signalled;
rscreen->screen.fence_finish = r600_fence_finish;
r600_init_screen_resource_functions(&rscreen->screen);
+ if (rscreen->info.has_uvd) {
+ rscreen->screen.get_video_param = ruvd_get_video_param;
+ rscreen->screen.is_video_format_supported = ruvd_is_format_supported;
+ } else {
+ rscreen->screen.get_video_param = r600_get_video_param;
+ rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
+ }
+
util_format_s3tc_init();
rscreen->fences.bo = NULL;
LIST_INITHEAD(&rscreen->fences.blocks);
pipe_mutex_init(rscreen->fences.mutex);
+#if R600_TRACE_CS
+ rscreen->cs_count = 0;
+ if (rscreen->info.drm_minor >= 28) {
+ rscreen->trace_bo = (struct si_resource*)pipe_buffer_create(&rscreen->screen,
+ PIPE_BIND_CUSTOM,
+ PIPE_USAGE_STAGING,
+ 4096);
+ if (rscreen->trace_bo) {
+ rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
+ PIPE_TRANSFER_UNSYNCHRONIZED);
+ }
+ }
+#endif
+
return &rscreen->screen;
}
projects / mesa.git / blobdiff