#include "util/u_pack_color.h"
#include "util/u_memory.h"
#include "util/u_inlines.h"
+#include "util/u_simple_shaders.h"
#include "util/u_upload_mgr.h"
#include "vl/vl_decoder.h"
#include "vl/vl_video_buffer.h"
pipe_reference_init(&fence->reference, 1);
rscreen->fences.data[fence->index] = 0;
- r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
+ si_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
/* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
fence->sleep_bo = si_resource_create_custom(&rctx->screen->screen, PIPE_USAGE_STAGING, 1);
ctx->render_condition(ctx, NULL, 0);
}
- r600_context_flush(rctx, flags);
+ si_context_flush(rctx, flags);
/* Re-enable render condition. */
if (render_cond) {
}
static void r600_flush_from_st(struct pipe_context *ctx,
- struct pipe_fence_handle **fence)
+ struct pipe_fence_handle **fence,
+ enum pipe_flush_flags flags)
{
radeonsi_flush(ctx, fence, 0);
}
{
struct r600_context *rctx = (struct r600_context *)context;
+ si_resource_reference(&rctx->border_color_table, NULL);
+
+ if (rctx->dummy_pixel_shader) {
+ rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
+ }
rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
util_unreference_framebuffer_state(&rctx->framebuffer);
rctx->family = rscreen->family;
rctx->chip_class = rscreen->chip_class;
- r600_init_blit_functions(rctx);
+ si_init_blit_functions(rctx);
r600_init_query_functions(rctx);
r600_init_context_resource_functions(rctx);
- r600_init_surface_functions(rctx);
+ si_init_surface_functions(rctx);
rctx->context.create_video_decoder = vl_create_decoder;
rctx->context.create_video_buffer = vl_video_buffer_create;
- r600_init_common_atoms(rctx);
-
switch (rctx->chip_class) {
case TAHITI:
si_init_state_functions(rctx);
- if (si_context_init(rctx)) {
- r600_destroy_context(&rctx->context);
- return NULL;
- }
+ LIST_INITHEAD(&rctx->active_query_list);
+ rctx->cs = rctx->ws->cs_create(rctx->ws);
+ rctx->max_db = 8;
si_init_config(rctx);
break;
default:
return NULL;
}
- LIST_INITHEAD(&rctx->dirty_states);
+ si_get_backend_mask(rctx); /* this emits commands and must be last */
- r600_get_backend_mask(rctx); /* this emits commands and must be last */
+ rctx->dummy_pixel_shader =
+ util_make_fragment_cloneinput_shader(&rctx->context, 0,
+ TGSI_SEMANTIC_GENERIC,
+ TGSI_INTERPOLATE_CONSTANT);
+ rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
return &rctx->context;
}
static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
{
struct r600_screen *rscreen = (struct r600_screen *)pscreen;
- enum radeon_family family = rscreen->family;
switch (param) {
/* Supported features (boolean caps). */
- case PIPE_CAP_NPOT_TEXTURES:
case PIPE_CAP_TWO_SIDED_STENCIL:
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
case PIPE_CAP_ANISOTROPIC_FILTER:
case PIPE_CAP_USER_INDEX_BUFFERS:
case PIPE_CAP_USER_CONSTANT_BUFFERS:
case PIPE_CAP_START_INSTANCE:
+ case PIPE_CAP_NPOT_TEXTURES:
return 1;
+ case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
+ return 64;
+
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 256;
case PIPE_CAP_VERTEX_COLOR_CLAMPED:
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
case PIPE_CAP_USER_VERTEX_BUFFERS:
+ case PIPE_CAP_TEXTURE_MULTISAMPLE:
+ case PIPE_CAP_COMPUTE:
+ case PIPE_CAP_QUERY_TIMESTAMP:
+ case PIPE_CAP_CUBE_MAP_ARRAY:
+ case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
return 0;
/* Stream output. */
+#if 0
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0;
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
return 16*4;
+#endif
+ case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
+ case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
+ case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
+ case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
+ return 0;
/* Texturing. */
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
return 15;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
- return rscreen->info.drm_minor >= 9 ? 16384 : 0;
+ return /*rscreen->info.drm_minor >= 9 ? 16384 :*/ 0;
case PIPE_CAP_MAX_COMBINED_SAMPLERS:
return 32;
return 8;
/* Timer queries, present when the clock frequency is non zero. */
- case PIPE_CAP_TIMER_QUERY:
+ case PIPE_CAP_QUERY_TIME_ELAPSED:
return rscreen->info.r600_clock_crystal_freq != 0;
case PIPE_CAP_MIN_TEXEL_OFFSET:
static float r600_get_paramf(struct pipe_screen* pscreen,
enum pipe_capf param)
{
- struct r600_screen *rscreen = (struct r600_screen *)pscreen;
- enum radeon_family family = rscreen->family;
-
switch (param) {
case PIPE_CAPF_MAX_LINE_WIDTH:
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
{
- struct r600_screen *rscreen = (struct r600_screen *)pscreen;
switch(shader)
{
case PIPE_SHADER_FRAGMENT:
/* FIXME Isn't this equal to TEMPS? */
return 1; /* Max native address registers */
case PIPE_SHADER_CAP_MAX_CONSTS:
- return R600_MAX_CONST_BUFFER_SIZE;
+ return 64;
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
- return R600_MAX_CONST_BUFFERS;
+ return 1;
case PIPE_SHADER_CAP_MAX_PREDS:
return 0; /* FIXME */
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
return 16;
+ case PIPE_SHADER_CAP_PREFERRED_IR:
+ return PIPE_SHADER_IR_TGSI;
}
return 0;
}
struct r600_screen *rscreen = (struct r600_screen *)pscreen;
struct r600_fence *rfence = (struct r600_fence*)fence;
- return rscreen->fences.data[rfence->index];
+ return rscreen->fences.data[rfence->index] != 0;
}
static boolean r600_fence_finish(struct pipe_screen *pscreen,
projects / mesa.git / blobdiff