gallium: add TGSI_SEMANTIC_TEXCOORD,PCOORD v3

[mesa.git] / src / gallium / drivers / radeonsi / radeonsi_pipe.c

diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
index e069f1f2203b0dca03f5959d7c1b36dc6578d854..859843867ce926d3ae787c4f614fd2051a7bfeae 100644 (file)
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
@@ -158,9 +158,11 @@ void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 }
 
 static void r600_flush_from_st(struct pipe_context *ctx,
-                              struct pipe_fence_handle **fence)
+                              struct pipe_fence_handle **fence,
+                               enum pipe_flush_flags flags)
 {
-       radeonsi_flush(ctx, fence, 0);
+       radeonsi_flush(ctx, fence,
+                       flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
 }
 
 static void r600_flush_from_winsys(void *ctx, unsigned flags)
@@ -177,7 +179,10 @@ static void r600_destroy_context(struct pipe_context *context)
        if (rctx->dummy_pixel_shader) {
                rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
        }
-       rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
+       rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_depth_stencil);
+       rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_depth);
+       rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_stencil);
+       rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_inplace);
        util_unreference_framebuffer_state(&rctx->framebuffer);
 
        util_blitter_destroy(rctx->blitter);
@@ -220,7 +225,7 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
        case TAHITI:
                si_init_state_functions(rctx);
                LIST_INITHEAD(&rctx->active_query_list);
-               rctx->cs = rctx->ws->cs_create(rctx->ws);
+               rctx->cs = rctx->ws->cs_create(rctx->ws, RING_GFX);
                rctx->max_db = 8;
                si_init_config(rctx);
                break;
@@ -275,6 +280,7 @@ static const char *r600_get_family_name(enum radeon_family family)
        case CHIP_TAHITI: return "AMD TAHITI";
        case CHIP_PITCAIRN: return "AMD PITCAIRN";
        case CHIP_VERDE: return "AMD CAPE VERDE";
+       case CHIP_OLAND: return "AMD OLAND";
        default: return "AMD unknown";
        }
 }
@@ -301,7 +307,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
        case PIPE_CAP_BLEND_EQUATION_SEPARATE:
        case PIPE_CAP_TEXTURE_SWIZZLE:
-       case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
        case PIPE_CAP_DEPTH_CLIP_DISABLE:
        case PIPE_CAP_SHADER_STENCIL_EXPORT:
        case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
@@ -325,6 +330,11 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_START_INSTANCE:
        case PIPE_CAP_NPOT_TEXTURES:
                return 1;
+       case PIPE_CAP_TGSI_TEXCOORD:
+               return 0;
+
+        case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
+                return 64;
 
        case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
                return 256;
@@ -346,6 +356,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_TEXTURE_MULTISAMPLE:
        case PIPE_CAP_COMPUTE:
        case PIPE_CAP_QUERY_TIMESTAMP:
+       case PIPE_CAP_CUBE_MAP_ARRAY:
+       case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
+       case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
                return 0;
 
        /* Stream output. */
@@ -370,7 +383,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
                        return 15;
        case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
-               return /*rscreen->info.drm_minor >= 9 ? 16384 :*/ 0;
+               return 16384;
        case PIPE_CAP_MAX_COMBINED_SAMPLERS:
                return 32;
 
@@ -380,7 +393,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return 8;
 
        /* Timer queries, present when the clock frequency is non zero. */
-       case PIPE_CAP_TIMER_QUERY:
+       case PIPE_CAP_QUERY_TIME_ELAPSED:
                return rscreen->info.r600_clock_crystal_freq != 0;
 
        case PIPE_CAP_MIN_TEXEL_OFFSET:
@@ -429,7 +442,6 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
                return 0;
        }
 
-       /* TODO: all these should be fixed, since r600 surely supports much more! */
        switch (param) {
        case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
        case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
@@ -437,30 +449,29 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
        case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
                return 16384;
        case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
-               return 8; /* FIXME */
+               return 32;
        case PIPE_SHADER_CAP_MAX_INPUTS:
-               if(shader == PIPE_SHADER_FRAGMENT)
-                       return 34;
-               else
-                       return 32;
+               return 32;
        case PIPE_SHADER_CAP_MAX_TEMPS:
                return 256; /* Max native temporaries. */
        case PIPE_SHADER_CAP_MAX_ADDRS:
                /* FIXME Isn't this equal to TEMPS? */
                return 1; /* Max native address registers */
        case PIPE_SHADER_CAP_MAX_CONSTS:
-               return 64;
+               return 4096; /* actually only memory limits this */
        case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
                return 1;
        case PIPE_SHADER_CAP_MAX_PREDS:
                return 0; /* FIXME */
        case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
                return 1;
+       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
+               return 0;
        case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
        case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
        case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
        case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
-               return 0;
+               return 1;
        case PIPE_SHADER_CAP_INTEGERS:
                return 1;
        case PIPE_SHADER_CAP_SUBROUTINES:
@@ -540,7 +551,7 @@ static boolean r600_fence_signalled(struct pipe_screen *pscreen,
        struct r600_screen *rscreen = (struct r600_screen *)pscreen;
        struct r600_fence *rfence = (struct r600_fence*)fence;
 
-       return rscreen->fences.data[rfence->index];
+       return rscreen->fences.data[rfence->index] != 0;
 }
 
 static boolean r600_fence_finish(struct pipe_screen *pscreen,