radeonsi: If pixel shader compilation fails, use a dummy shader.

[mesa.git] / src / gallium / drivers / radeonsi / radeonsi_shader.c

diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index 66050d3fd3ea404aace191173686a2cffda63470..a05061765efebbf9317ac0b1c3f52882368f61b6 100644 (file)
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c
@@ -1,6 +1,7 @@
 
 #include "gallivm/lp_bld_tgsi_action.h"
 #include "gallivm/lp_bld_const.h"
+#include "gallivm/lp_bld_gather.h"
 #include "gallivm/lp_bld_intr.h"
 #include "gallivm/lp_bld_tgsi.h"
 #include "radeon_llvm.h"
@@ -355,6 +356,8 @@ static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
                                &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
        struct tgsi_parse_context *parse = &si_shader_ctx->parse;
        LLVMValueRef last_args[9] = { 0 };
+       unsigned color_count = 0;
+       unsigned param_count = 0;
 
        while (!tgsi_parse_end_of_tokens(parse)) {
                /* XXX: component_bits controls which components of the output
@@ -369,8 +372,6 @@ static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
                LLVMValueRef args[9];
                unsigned target;
                unsigned index;
-               unsigned color_count = 0;
-               unsigned param_count = 0;
                int i;
 
                tgsi_parse_token(parse);
@@ -384,17 +385,18 @@ static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
                        shader->input[i].sid = d->Semantic.Index;
                        shader->input[i].interpolate = d->Interp.Interpolate;
                        shader->input[i].centroid = d->Interp.Centroid;
-                       break;
+                       continue;
+
                case TGSI_FILE_OUTPUT:
                        i = shader->noutput++;
                        shader->output[i].name = d->Semantic.Name;
                        shader->output[i].sid = d->Semantic.Index;
                        shader->output[i].interpolate = d->Interp.Interpolate;
                        break;
-               }
 
-               if (d->Declaration.File != TGSI_FILE_OUTPUT)
+               default:
                        continue;
+               }
 
                for (index = d->Range.First; index <= d->Range.Last; index++) {
                        for (chan = 0; chan < 4; chan++ ) {
@@ -475,6 +477,25 @@ static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
                }
        }
 
+       if (!last_args[0]) {
+               assert(si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
+
+               /* Specify which components to enable */
+               last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
+
+               /* Specify the target we are exporting */
+               last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
+
+               /* Set COMPR flag to zero to export data as 32-bit */
+               last_args[4] = uint->zero;
+
+               /* dummy bits */
+               last_args[5]= uint->zero;
+               last_args[6]= uint->zero;
+               last_args[7]= uint->zero;
+               last_args[8]= uint->zero;
+       }
+
        /* Specify whether the EXEC mask represents the valid mask */
        last_args[1] = lp_build_const_int32(base->gallivm,
                                            si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
@@ -495,29 +516,49 @@ static void tex_fetch_args(
        struct lp_build_tgsi_context * bld_base,
        struct lp_build_emit_data * emit_data)
 {
+       const struct tgsi_full_instruction * inst = emit_data->inst;
        LLVMValueRef ptr;
        LLVMValueRef offset;
 
        /* WriteMask */
-       emit_data->args[0] = lp_build_const_int32(bld_base->base.gallivm,
-                               emit_data->inst->Dst[0].Register.WriteMask);
+       /* XXX: should be optimized using emit_data->inst->Dst[0].Register.WriteMask*/
+       emit_data->args[0] = lp_build_const_int32(bld_base->base.gallivm, 0xf);
 
        /* Coordinates */
        /* XXX: Not all sample instructions need 4 address arguments. */
-       emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
-                                                       0, LP_CHAN_ALL);
+       if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
+               LLVMValueRef src_w;
+               unsigned chan;
+               LLVMValueRef coords[4];
+
+               emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
+               src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
+
+               for (chan = 0; chan < 3; chan++ ) {
+                       LLVMValueRef arg = lp_build_emit_fetch(bld_base,
+                                                              emit_data->inst, 0, chan);
+                       coords[chan] = lp_build_emit_llvm_binary(bld_base,
+                                                                TGSI_OPCODE_DIV,
+                                                                arg, src_w);
+               }
+               coords[3] = bld_base->base.one;
+               emit_data->args[1] = lp_build_gather_values(bld_base->base.gallivm,
+                                                           coords, 4);
+       } else
+               emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
+                                                        0, LP_CHAN_ALL);
 
        /* Resource */
        ptr = use_sgpr(bld_base->base.gallivm, SGPR_CONST_PTR_V8I32, 4);
        offset = lp_build_const_int32(bld_base->base.gallivm,
-                                 8 * emit_data->inst->Src[1].Register.Index);
+                                 emit_data->inst->Src[1].Register.Index);
        emit_data->args[2] = build_indexed_load(bld_base->base.gallivm,
                                                ptr, offset);
 
        /* Sampler */
        ptr = use_sgpr(bld_base->base.gallivm, SGPR_CONST_PTR_V4I32, 2);
        offset = lp_build_const_int32(bld_base->base.gallivm,
-                                 4 * emit_data->inst->Src[1].Register.Index);
+                                 emit_data->inst->Src[1].Register.Index);
        emit_data->args[3] = build_indexed_load(bld_base->base.gallivm,
                                                ptr, offset);
 
@@ -559,6 +600,7 @@ int si_pipe_shader_create(
 
        dump = debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE);
 
+       memset(&si_shader_ctx.radeon_bld, 0, sizeof(si_shader_ctx.radeon_bld));
        radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
        bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
 
@@ -568,6 +610,7 @@ int si_pipe_shader_create(
        bld_base->emit_epilogue = si_llvm_emit_epilogue;
 
        bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
+       bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
 
        si_shader_ctx.radeon_bld.load_input = declare_input;
        si_shader_ctx.tokens = shader->tokens;
@@ -584,7 +627,10 @@ int si_pipe_shader_create(
                tgsi_dump(shader->tokens, 0);
        }
 
-       lp_build_tgsi_llvm(bld_base, shader->tokens);
+       if (!lp_build_tgsi_llvm(bld_base, shader->tokens)) {
+               fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
+               return -EINVAL;
+       }
 
        radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);