radeonsi: remove r600_pipe_common::decompress_dcc
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
index f1c4f6d1e723f16a03551413314da7bfc1f314bb..27221714a40ea0591e3efa3f966bcfe1e234fe4c 100644 (file)
@@ -713,6 +713,11 @@ static void si_check_render_feedback_resident_images(struct si_context *sctx)
 
 static void si_check_render_feedback(struct si_context *sctx)
 {
+       /* There is no render feedback if color writes are disabled.
+        * (e.g. a pixel shader with image stores)
+        */
+       if (!si_get_total_colormask(sctx))
+               return;
 
        if (!sctx->need_check_render_feedback)
                return;
@@ -806,6 +811,14 @@ void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
                        si_decompress_resident_images(sctx);
        }
 
+       if (sctx->ps_uses_fbfetch) {
+               struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
+               si_decompress_color_texture(sctx,
+                                           (struct r600_texture*)cb0->texture,
+                                           cb0->u.tex.first_layer,
+                                           cb0->u.tex.last_layer);
+       }
+
        si_check_render_feedback(sctx);
 }
 
@@ -1312,8 +1325,7 @@ static void si_flush_resource(struct pipe_context *ctx,
        }
 }
 
-static void si_decompress_dcc(struct pipe_context *ctx,
-                             struct r600_texture *rtex)
+void si_decompress_dcc(struct pipe_context *ctx, struct r600_texture *rtex)
 {
        if (!rtex->dcc_offset)
                return;
@@ -1330,5 +1342,4 @@ void si_init_blit_functions(struct si_context *sctx)
        sctx->b.b.flush_resource = si_flush_resource;
        sctx->b.b.generate_mipmap = si_generate_mipmap;
        sctx->b.blit_decompress_depth = si_blit_decompress_depth;
-       sctx->b.decompress_dcc = si_decompress_dcc;
 }