static void si_alloc_separate_cmask(struct si_screen *sscreen,
struct si_texture *tex)
{
- if (tex->cmask_buffer)
+ /* CMASK for MSAA is allocated in advance or always disabled
+ * by "nofmask" option.
+ */
+ if (tex->cmask_buffer || !tex->surface.cmask_size ||
+ tex->buffer.b.b.nr_samples >= 2)
return;
- assert(tex->cmask.size == 0);
-
- si_texture_get_cmask_info(sscreen, tex, &tex->cmask);
- if (!tex->cmask.size)
- return;
-
tex->cmask_buffer =
si_aligned_buffer_create(&sscreen->b,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
- tex->cmask.size,
- tex->cmask.alignment);
- if (tex->cmask_buffer == NULL) {
- tex->cmask.size = 0;
+ tex->surface.cmask_size,
+ tex->surface.cmask_alignment);
+ if (tex->cmask_buffer == NULL)
return;
- }
-
- /* update colorbuffer state bits */
- tex->cmask.base_address_reg = tex->cmask_buffer->gpu_address >> 8;
+ tex->cmask_base_address_reg = tex->cmask_buffer->gpu_address >> 8;
tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
p_atomic_inc(&sscreen->compressed_colortex_counter);
return util_format_intensity_to_red(format);
}
-bool vi_alpha_is_on_msb(enum pipe_format format)
+bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format)
{
format = si_simplify_cb_format(format);
+ const struct util_format_description *desc = util_format_description(format);
/* Formats with 3 channels can't have alpha. */
- if (util_format_description(format)->nr_channels == 3)
+ if (desc->nr_channels == 3)
return true; /* same as xxxA; is any value OK here? */
+ if (sscreen->info.chip_class >= GFX10 && desc->nr_channels == 1)
+ return desc->swizzle[3] == PIPE_SWIZZLE_X;
+
return si_translate_colorswap(format, false) <= 1;
}
-static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
+static bool vi_get_fast_clear_parameters(struct si_screen *sscreen,
+ enum pipe_format base_format,
enum pipe_format surface_format,
const union pipe_color_union *color,
uint32_t* clear_value,
return false;
*eliminate_needed = true;
- *clear_value = 0x20202020U; /* use CB clear color registers */
+ *clear_value = DCC_CLEAR_COLOR_REG;
if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
return true; /* need ELIMINATE_FAST_CLEAR */
- bool base_alpha_is_on_msb = vi_alpha_is_on_msb(base_format);
- bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(surface_format);
+ bool base_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, base_format);
+ bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, surface_format);
/* Formats with 3 channels can't have alpha. */
if (desc->nr_channels == 3)
}
/* This doesn't need ELIMINATE_FAST_CLEAR.
- * CB uses both the DCC clear codes and the CB clear color registers,
- * so they must match.
+ * On chips predating Raven2, the DCC clear codes and the CB clear
+ * color registers must match.
*/
*eliminate_needed = false;
- if (color_value)
- *clear_value |= 0x80808080U;
- if (alpha_value)
- *clear_value |= 0x40404040U;
+ if (color_value) {
+ if (alpha_value)
+ *clear_value = DCC_CLEAR_COLOR_1111;
+ else
+ *clear_value = DCC_CLEAR_COLOR_1110;
+ } else {
+ if (alpha_value)
+ *clear_value = DCC_CLEAR_COLOR_0001;
+ else
+ *clear_value = DCC_CLEAR_COLOR_0000;
+ }
return true;
}
assert(tex->buffer.b.b.last_level == 0);
/* 4x and 8x MSAA needs a sophisticated compute shader for
* the clear. See AMDVLK. */
- assert(tex->num_color_samples <= 2);
+ assert(tex->buffer.b.b.nr_storage_samples <= 2);
clear_size = tex->surface.dcc_size;
} else {
unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
* dcc_fast_clear_size bytes for each layer. A compute shader
* would be more efficient than separate per-layer clear operations.
*/
- assert(tex->num_color_samples <= 2 || num_layers == 1);
+ assert(tex->buffer.b.b.nr_storage_samples <= 2 || num_layers == 1);
dcc_offset += tex->surface.u.legacy.level[level].dcc_offset;
clear_size = tex->surface.u.legacy.level[level].dcc_fast_clear_size *
}
si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
- clear_value, SI_COHERENCY_CB_META);
+ &clear_value, 4, SI_COHERENCY_CB_META, false);
}
/* Set the same micro tile mode as the destination of the last MSAA resolve.
static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
struct si_texture *tex)
{
- if (tex->buffer.b.is_shared ||
+ if (sscreen->info.chip_class >= GFX10 ||
+ tex->buffer.b.is_shared ||
tex->buffer.b.b.nr_samples <= 1 ||
tex->surface.micro_tile_mode == tex->last_msaa_resolve_target_micro_mode)
return;
assert(!"unexpected micro mode");
return;
}
- } else if (sscreen->info.chip_class >= CIK) {
+ } else if (sscreen->info.chip_class >= GFX7) {
/* These magic numbers were copied from addrlib. It doesn't use
* any definitions for them either. They are all 2D_TILED_THIN1
* modes with different bpp and micro tile mode.
assert(!"unexpected micro mode");
return;
}
- } else { /* SI */
+ } else { /* GFX6 */
switch (tex->last_msaa_resolve_target_micro_mode) {
case RADEON_MICRO_MODE_DISPLAY:
switch (tex->surface.bpe) {
!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
continue;
- if (sctx->chip_class <= VI &&
+ if (sctx->chip_class <= GFX8 &&
tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
!sctx->screen->info.htile_cmask_support_1d_tiling)
continue;
+ /* Use a slow clear for small surfaces where the cost of
+ * the eliminate pass can be higher than the benefit of fast
+ * clear. The closed driver does this, but the numbers may differ.
+ *
+ * This helps on both dGPUs and APUs, even small APUs like Mullins.
+ */
+ bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
+ tex->buffer.b.b.width0 *
+ tex->buffer.b.b.height0 <= 512 * 512;
+ bool eliminate_needed = false;
+ bool fmask_decompress_needed = false;
+
/* Fast clear is the most appropriate place to enable DCC for
* displayable surfaces.
*/
- if (sctx->chip_class >= VI &&
- !(sctx->screen->debug_flags & DBG(NO_DCC_FB))) {
+ if (sctx->family == CHIP_STONEY && !too_small) {
vi_separate_dcc_try_enable(sctx, tex);
/* RB+ isn't supported with a CMASK clear only on Stoney,
* clears, which is weighed when determining whether to
* enable separate DCC.
*/
- if (tex->dcc_gather_statistics &&
- sctx->family == CHIP_STONEY)
+ if (tex->dcc_gather_statistics) /* only for Stoney */
tex->num_slow_clears++;
}
- bool need_decompress_pass = false;
-
- /* Use a slow clear for small surfaces where the cost of
- * the eliminate pass can be higher than the benefit of fast
- * clear. The closed driver does this, but the numbers may differ.
- *
- * This helps on both dGPUs and APUs, even small APUs like Mullins.
- */
- bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
- tex->buffer.b.b.width0 *
- tex->buffer.b.b.height0 <= 512 * 512;
-
/* Try to clear DCC first, otherwise try CMASK. */
if (vi_dcc_enabled(tex, 0)) {
uint32_t reset_value;
- bool eliminate_needed;
if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
continue;
/* This can happen with mipmapping or MSAA. */
- if (sctx->chip_class == VI &&
+ if (sctx->chip_class == GFX8 &&
!tex->surface.u.legacy.level[level].dcc_fast_clear_size)
continue;
- if (!vi_get_fast_clear_parameters(tex->buffer.b.b.format,
+ if (!vi_get_fast_clear_parameters(sctx->screen,
+ tex->buffer.b.b.format,
fb->cbufs[i]->format,
color, &reset_value,
&eliminate_needed))
continue;
/* DCC fast clear with MSAA should clear CMASK to 0xC. */
- if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask.size) {
+ if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) {
/* TODO: This doesn't work with MSAA. */
if (eliminate_needed)
continue;
+ uint32_t clear_value = 0xCCCCCCCC;
si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
- tex->cmask.offset, tex->cmask.size,
- 0xCCCCCCCC, SI_COHERENCY_CB_META);
- need_decompress_pass = true;
+ tex->cmask_offset, tex->surface.cmask_size,
+ &clear_value, 4, SI_COHERENCY_CB_META, false);
+ fmask_decompress_needed = true;
}
vi_dcc_clear_level(sctx, tex, 0, reset_value);
-
- if (eliminate_needed)
- need_decompress_pass = true;
-
tex->separate_dcc_dirty = true;
} else {
if (too_small)
/* ensure CMASK is enabled */
si_alloc_separate_cmask(sctx->screen, tex);
- if (tex->cmask.size == 0) {
+ if (!tex->cmask_buffer)
continue;
- }
/* Do the fast clear. */
+ uint32_t clear_value = 0;
si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
- tex->cmask.offset, tex->cmask.size, 0,
- SI_COHERENCY_CB_META);
- need_decompress_pass = true;
+ tex->cmask_offset, tex->surface.cmask_size,
+ &clear_value, 4, SI_COHERENCY_CB_META, false);
+ eliminate_needed = true;
}
- if (need_decompress_pass &&
+ if ((eliminate_needed || fmask_decompress_needed) &&
!(tex->dirty_level_mask & (1 << level))) {
tex->dirty_level_mask |= 1 << level;
p_atomic_inc(&sctx->screen->compressed_colortex_counter);
/* We can change the micro tile mode before a full clear. */
si_set_optimal_micro_tile_mode(sctx->screen, tex);
+ *buffers &= ~clear_bit;
+
+ /* Chips with DCC constant encoding don't need to set the clear
+ * color registers for DCC clear values 0 and 1.
+ */
+ if (sctx->screen->has_dcc_constant_encode && !eliminate_needed)
+ continue;
+
if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
sctx->framebuffer.dirty_cbufs |= 1 << i;
si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
}
- *buffers &= ~clear_bit;
}
}
}
if (zstex &&
- si_htile_enabled(zstex, zsbuf->u.tex.level) &&
zsbuf->u.tex.first_layer == 0 &&
zsbuf->u.tex.last_layer == util_max_layer(&zstex->buffer.b.b, 0)) {
/* TC-compatible HTILE only supports depth clears to 0 or 1. */
if (buffers & PIPE_CLEAR_DEPTH &&
+ si_htile_enabled(zstex, zsbuf->u.tex.level, PIPE_MASK_Z) &&
(!zstex->tc_compatible_htile ||
depth == 0 || depth == 1)) {
/* Need to disable EXPCLEAR temporarily if clearing
/* TC-compatible HTILE only supports stencil clears to 0. */
if (buffers & PIPE_CLEAR_STENCIL &&
+ si_htile_enabled(zstex, zsbuf->u.tex.level, PIPE_MASK_S) &&
(!zstex->tc_compatible_htile || stencil == 0)) {
stencil &= 0xff;
* This hack decreases back-to-back ClearDepth performance.
*/
if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
- sctx->screen->clear_db_cache_before_clear)
+ sctx->screen->options.clear_db_cache_before_clear)
sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
}
bool render_condition_enabled)
{
struct si_context *sctx = (struct si_context *)ctx;
+ struct si_texture *sdst = (struct si_texture*)dst->texture;
+
+ if (dst->texture->nr_samples <= 1 && !sdst->dcc_offset) {
+ si_compute_clear_render_target(ctx, dst, color, dstx, dsty, width,
+ height, render_condition_enabled);
+ return;
+ }
si_blitter_begin(sctx, SI_CLEAR_SURFACE |
(render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
if (screen->is_format_supported(screen, tex->format,
- tex->target, 0,
+ tex->target, 0, 0,
PIPE_BIND_RENDER_TARGET)) {
si_clear_render_target(pipe, sf, &color,
box->x, box->y,
void si_init_clear_functions(struct si_context *sctx)
{
- sctx->b.clear = si_clear;
sctx->b.clear_render_target = si_clear_render_target;
- sctx->b.clear_depth_stencil = si_clear_depth_stencil;
sctx->b.clear_texture = si_clear_texture;
+
+ if (sctx->has_graphics) {
+ sctx->b.clear = si_clear;
+ sctx->b.clear_depth_stencil = si_clear_depth_stencil;
+ }
}
projects / mesa.git / blobdiff