radeonsi: use si_set_rw_shader_buffer for setting streamout buffers

[mesa.git] / src / gallium / drivers / radeonsi / si_clear.c

diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 8aa3355afc8f8e9d28fcdbcdeb1e560bfcbf4a75..9026f61dc0a754d48821ec15baecebedf6d3b41d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -34,6 +34,15 @@ enum {
        SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
 };
 
+enum si_dcc_clear_code
+{
+       DCC_CLEAR_COLOR_0000   = 0x00000000,
+       DCC_CLEAR_COLOR_0001   = 0x40404040,
+       DCC_CLEAR_COLOR_1110   = 0x80808080,
+       DCC_CLEAR_COLOR_1111   = 0xC0C0C0C0,
+       DCC_CLEAR_COLOR_REG    = 0x20202020,
+};
+
 static void si_alloc_separate_cmask(struct si_screen *sscreen,
                                    struct si_texture *tex)
 {
@@ -133,7 +142,7 @@ static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
                return false;
 
        *eliminate_needed = true;
-       *clear_value = 0x20202020U; /* use CB clear color registers */
+       *clear_value = DCC_CLEAR_COLOR_REG;
 
        if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
                return true; /* need ELIMINATE_FAST_CLEAR */
@@ -203,15 +212,22 @@ static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
        }
 
        /* This doesn't need ELIMINATE_FAST_CLEAR.
-        * CB uses both the DCC clear codes and the CB clear color registers,
-        * so they must match.
+        * On chips predating Raven2, the DCC clear codes and the CB clear
+        * color registers must match.
         */
        *eliminate_needed = false;
 
-       if (color_value)
-               *clear_value |= 0x80808080U;
-       if (alpha_value)
-               *clear_value |= 0x40404040U;
+       if (color_value) {
+               if (alpha_value)
+                       *clear_value = DCC_CLEAR_COLOR_1111;
+               else
+                       *clear_value = DCC_CLEAR_COLOR_1110;
+       } else {
+               if (alpha_value)
+                       *clear_value = DCC_CLEAR_COLOR_0001;
+               else
+                       *clear_value = DCC_CLEAR_COLOR_0000;
+       }
        return true;
 }
 
@@ -532,6 +548,12 @@ static void si_do_fast_color_clear(struct si_context *sctx,
 
                *buffers &= ~clear_bit;
 
+               /* Chips with DCC constant encoding don't need to set the clear
+                * color registers for DCC clear values 0 and 1.
+                */
+               if (sctx->screen->has_dcc_constant_encode && !eliminate_needed)
+                       continue;
+
                if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
                        sctx->framebuffer.dirty_cbufs |= 1 << i;
                        si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);