radeonsi: add an si_set_rw_shader_buffer convenience function

[mesa.git] / src / gallium / drivers / radeonsi / si_clear.c

diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 520e5b94f4a6b49d78387ba56818a2de7e0efe0d..9026f61dc0a754d48821ec15baecebedf6d3b41d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -34,6 +34,15 @@ enum {
        SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
 };
 
+enum si_dcc_clear_code
+{
+       DCC_CLEAR_COLOR_0000   = 0x00000000,
+       DCC_CLEAR_COLOR_0001   = 0x40404040,
+       DCC_CLEAR_COLOR_1110   = 0x80808080,
+       DCC_CLEAR_COLOR_1111   = 0xC0C0C0C0,
+       DCC_CLEAR_COLOR_REG    = 0x20202020,
+};
+
 static void si_alloc_separate_cmask(struct si_screen *sscreen,
                                    struct si_texture *tex)
 {
@@ -133,7 +142,7 @@ static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
                return false;
 
        *eliminate_needed = true;
-       *clear_value = 0x20202020U; /* use CB clear color registers */
+       *clear_value = DCC_CLEAR_COLOR_REG;
 
        if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
                return true; /* need ELIMINATE_FAST_CLEAR */
@@ -203,15 +212,22 @@ static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
        }
 
        /* This doesn't need ELIMINATE_FAST_CLEAR.
-        * CB uses both the DCC clear codes and the CB clear color registers,
-        * so they must match.
+        * On chips predating Raven2, the DCC clear codes and the CB clear
+        * color registers must match.
         */
        *eliminate_needed = false;
 
-       if (color_value)
-               *clear_value |= 0x80808080U;
-       if (alpha_value)
-               *clear_value |= 0x40404040U;
+       if (color_value) {
+               if (alpha_value)
+                       *clear_value = DCC_CLEAR_COLOR_1111;
+               else
+                       *clear_value = DCC_CLEAR_COLOR_1110;
+       } else {
+               if (alpha_value)
+                       *clear_value = DCC_CLEAR_COLOR_0001;
+               else
+                       *clear_value = DCC_CLEAR_COLOR_0000;
+       }
        return true;
 }
 
@@ -432,8 +448,6 @@ static void si_do_fast_color_clear(struct si_context *sctx,
                    !sctx->screen->info.htile_cmask_support_1d_tiling)
                        continue;
 
-               bool need_decompress_pass = false;
-
                /* Use a slow clear for small surfaces where the cost of
                 * the eliminate pass can be higher than the benefit of fast
                 * clear. The closed driver does this, but the numbers may differ.
@@ -443,6 +457,8 @@ static void si_do_fast_color_clear(struct si_context *sctx,
                bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
                                 tex->buffer.b.b.width0 *
                                 tex->buffer.b.b.height0 <= 512 * 512;
+               bool eliminate_needed = false;
+               bool fmask_decompress_needed = false;
 
                /* Fast clear is the most appropriate place to enable DCC for
                 * displayable surfaces.
@@ -462,7 +478,6 @@ static void si_do_fast_color_clear(struct si_context *sctx,
                /* Try to clear DCC first, otherwise try CMASK. */
                if (vi_dcc_enabled(tex, 0)) {
                        uint32_t reset_value;
-                       bool eliminate_needed;
 
                        if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
                                continue;
@@ -491,14 +506,10 @@ static void si_do_fast_color_clear(struct si_context *sctx,
                                si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
                                                tex->cmask_offset, tex->surface.cmask_size,
                                                &clear_value, 4, SI_COHERENCY_CB_META);
-                               need_decompress_pass = true;
+                               fmask_decompress_needed = true;
                        }
 
                        vi_dcc_clear_level(sctx, tex, 0, reset_value);
-
-                       if (eliminate_needed)
-                               need_decompress_pass = true;
-
                        tex->separate_dcc_dirty = true;
                } else {
                        if (too_small)
@@ -523,10 +534,10 @@ static void si_do_fast_color_clear(struct si_context *sctx,
                        si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
                                        tex->cmask_offset, tex->surface.cmask_size,
                                        &clear_value, 4, SI_COHERENCY_CB_META);
-                       need_decompress_pass = true;
+                       eliminate_needed = true;
                }
 
-               if (need_decompress_pass &&
+               if ((eliminate_needed || fmask_decompress_needed) &&
                    !(tex->dirty_level_mask & (1 << level))) {
                        tex->dirty_level_mask |= 1 << level;
                        p_atomic_inc(&sctx->screen->compressed_colortex_counter);
@@ -535,11 +546,18 @@ static void si_do_fast_color_clear(struct si_context *sctx,
                /* We can change the micro tile mode before a full clear. */
                si_set_optimal_micro_tile_mode(sctx->screen, tex);
 
+               *buffers &= ~clear_bit;
+
+               /* Chips with DCC constant encoding don't need to set the clear
+                * color registers for DCC clear values 0 and 1.
+                */
+               if (sctx->screen->has_dcc_constant_encode && !eliminate_needed)
+                       continue;
+
                if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
                        sctx->framebuffer.dirty_cbufs |= 1 << i;
                        si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
                }
-               *buffers &= ~clear_bit;
        }
 }