};
static void si_alloc_separate_cmask(struct si_screen *sscreen,
- struct r600_texture *rtex)
+ struct si_texture *tex)
{
- if (rtex->cmask_buffer)
+ /* CMASK for MSAA is allocated in advance or always disabled
+ * by "nofmask" option.
+ */
+ if (tex->cmask_buffer || !tex->surface.cmask_size ||
+ tex->buffer.b.b.nr_samples >= 2)
return;
- assert(rtex->cmask.size == 0);
-
- si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask);
- if (!rtex->cmask.size)
- return;
-
- rtex->cmask_buffer =
+ tex->cmask_buffer =
si_aligned_buffer_create(&sscreen->b,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
- rtex->cmask.size,
- rtex->cmask.alignment);
- if (rtex->cmask_buffer == NULL) {
- rtex->cmask.size = 0;
+ tex->surface.cmask_size,
+ tex->surface.cmask_alignment);
+ if (tex->cmask_buffer == NULL)
return;
- }
- /* update colorbuffer state bits */
- rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
-
- rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
+ tex->cmask_base_address_reg = tex->cmask_buffer->gpu_address >> 8;
+ tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
p_atomic_inc(&sscreen->compressed_colortex_counter);
}
-static void si_set_clear_color(struct r600_texture *rtex,
+static bool si_set_clear_color(struct si_texture *tex,
enum pipe_format surface_format,
const union pipe_color_union *color)
{
memset(&uc, 0, sizeof(uc));
- if (rtex->surface.bpe == 16) {
+ if (tex->surface.bpe == 16) {
/* DCC fast clear only:
* CLEAR_WORD0 = R = G = B
* CLEAR_WORD1 = A
util_pack_color(color->f, surface_format, &uc);
}
- memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
+ if (memcmp(tex->color_clear_value, &uc, 2 * sizeof(uint32_t)) == 0)
+ return false;
+
+ memcpy(tex->color_clear_value, &uc, 2 * sizeof(uint32_t));
+ return true;
}
/** Linearize and convert luminace/intensity to red. */
return util_format_intensity_to_red(format);
}
-bool vi_alpha_is_on_msb(enum pipe_format format)
+bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format)
{
format = si_simplify_cb_format(format);
+ const struct util_format_description *desc = util_format_description(format);
/* Formats with 3 channels can't have alpha. */
- if (util_format_description(format)->nr_channels == 3)
+ if (desc->nr_channels == 3)
return true; /* same as xxxA; is any value OK here? */
+ if (sscreen->info.chip_class >= GFX10 && desc->nr_channels == 1)
+ return desc->swizzle[3] == PIPE_SWIZZLE_X;
+
return si_translate_colorswap(format, false) <= 1;
}
-static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
+static bool vi_get_fast_clear_parameters(struct si_screen *sscreen,
+ enum pipe_format base_format,
enum pipe_format surface_format,
const union pipe_color_union *color,
uint32_t* clear_value,
return false;
*eliminate_needed = true;
- *clear_value = 0x20202020U; /* use CB clear color registers */
+ *clear_value = DCC_CLEAR_COLOR_REG;
if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
return true; /* need ELIMINATE_FAST_CLEAR */
- bool base_alpha_is_on_msb = vi_alpha_is_on_msb(base_format);
- bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(surface_format);
+ bool base_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, base_format);
+ bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, surface_format);
/* Formats with 3 channels can't have alpha. */
if (desc->nr_channels == 3)
}
/* This doesn't need ELIMINATE_FAST_CLEAR.
- * CB uses both the DCC clear codes and the CB clear color registers,
- * so they must match.
+ * On chips predating Raven2, the DCC clear codes and the CB clear
+ * color registers must match.
*/
*eliminate_needed = false;
- if (color_value)
- *clear_value |= 0x80808080U;
- if (alpha_value)
- *clear_value |= 0x40404040U;
+ if (color_value) {
+ if (alpha_value)
+ *clear_value = DCC_CLEAR_COLOR_1111;
+ else
+ *clear_value = DCC_CLEAR_COLOR_1110;
+ } else {
+ if (alpha_value)
+ *clear_value = DCC_CLEAR_COLOR_0001;
+ else
+ *clear_value = DCC_CLEAR_COLOR_0000;
+ }
return true;
}
-void vi_dcc_clear_level(struct si_context *sctx,
- struct r600_texture *rtex,
+bool vi_dcc_clear_level(struct si_context *sctx,
+ struct si_texture *tex,
unsigned level, unsigned clear_value)
{
struct pipe_resource *dcc_buffer;
uint64_t dcc_offset, clear_size;
- assert(vi_dcc_enabled(rtex, level));
+ assert(vi_dcc_enabled(tex, level));
- if (rtex->dcc_separate_buffer) {
- dcc_buffer = &rtex->dcc_separate_buffer->b.b;
+ if (tex->dcc_separate_buffer) {
+ dcc_buffer = &tex->dcc_separate_buffer->b.b;
dcc_offset = 0;
} else {
- dcc_buffer = &rtex->buffer.b.b;
- dcc_offset = rtex->dcc_offset;
+ dcc_buffer = &tex->buffer.b.b;
+ dcc_offset = tex->dcc_offset;
}
if (sctx->chip_class >= GFX9) {
/* Mipmap level clears aren't implemented. */
- assert(rtex->buffer.b.b.last_level == 0);
+ if (tex->buffer.b.b.last_level > 0)
+ return false;
+
/* 4x and 8x MSAA needs a sophisticated compute shader for
* the clear. See AMDVLK. */
- assert(rtex->buffer.b.b.nr_samples <= 2);
- clear_size = rtex->surface.dcc_size;
+ if (tex->buffer.b.b.nr_storage_samples >= 4)
+ return false;
+
+ clear_size = tex->surface.dcc_size;
} else {
- unsigned num_layers = util_num_layers(&rtex->buffer.b.b, level);
+ unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
/* If this is 0, fast clear isn't possible. (can occur with MSAA) */
- assert(rtex->surface.u.legacy.level[level].dcc_fast_clear_size);
+ if (!tex->surface.u.legacy.level[level].dcc_fast_clear_size)
+ return false;
+
/* Layered 4x and 8x MSAA DCC fast clears need to clear
* dcc_fast_clear_size bytes for each layer. A compute shader
* would be more efficient than separate per-layer clear operations.
*/
- assert(rtex->buffer.b.b.nr_samples <= 2 || num_layers == 1);
+ if (tex->buffer.b.b.nr_storage_samples >= 4 && num_layers > 1)
+ return false;
- dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
- clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size *
+ dcc_offset += tex->surface.u.legacy.level[level].dcc_offset;
+ clear_size = tex->surface.u.legacy.level[level].dcc_fast_clear_size *
num_layers;
}
si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
- clear_value, SI_COHERENCY_CB_META);
+ &clear_value, 4, SI_COHERENCY_CB_META, false);
+ return true;
}
/* Set the same micro tile mode as the destination of the last MSAA resolve.
* src and dst micro tile modes match.
*/
static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
- struct r600_texture *rtex)
+ struct si_texture *tex)
{
- if (rtex->buffer.b.is_shared ||
- rtex->buffer.b.b.nr_samples <= 1 ||
- rtex->surface.micro_tile_mode == rtex->last_msaa_resolve_target_micro_mode)
+ if (sscreen->info.chip_class >= GFX10 ||
+ tex->buffer.b.is_shared ||
+ tex->buffer.b.b.nr_samples <= 1 ||
+ tex->surface.micro_tile_mode == tex->last_msaa_resolve_target_micro_mode)
return;
assert(sscreen->info.chip_class >= GFX9 ||
- rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
- assert(rtex->buffer.b.b.last_level == 0);
+ tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
+ assert(tex->buffer.b.b.last_level == 0);
if (sscreen->info.chip_class >= GFX9) {
/* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
- assert(rtex->surface.u.gfx9.surf.swizzle_mode >= 4);
+ assert(tex->surface.u.gfx9.surf.swizzle_mode >= 4);
/* If you do swizzle_mode % 4, you'll get:
* 0 = Depth
*
* Depth-sample order isn't allowed:
*/
- assert(rtex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
+ assert(tex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
- switch (rtex->last_msaa_resolve_target_micro_mode) {
+ switch (tex->last_msaa_resolve_target_micro_mode) {
case RADEON_MICRO_MODE_DISPLAY:
- rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
- rtex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
+ tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
+ tex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
break;
case RADEON_MICRO_MODE_THIN:
- rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
- rtex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
+ tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
+ tex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
break;
case RADEON_MICRO_MODE_ROTATED:
- rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
- rtex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
+ tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
+ tex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
break;
default: /* depth */
assert(!"unexpected micro mode");
return;
}
- } else if (sscreen->info.chip_class >= CIK) {
+ } else if (sscreen->info.chip_class >= GFX7) {
/* These magic numbers were copied from addrlib. It doesn't use
* any definitions for them either. They are all 2D_TILED_THIN1
* modes with different bpp and micro tile mode.
*/
- switch (rtex->last_msaa_resolve_target_micro_mode) {
+ switch (tex->last_msaa_resolve_target_micro_mode) {
case RADEON_MICRO_MODE_DISPLAY:
- rtex->surface.u.legacy.tiling_index[0] = 10;
+ tex->surface.u.legacy.tiling_index[0] = 10;
break;
case RADEON_MICRO_MODE_THIN:
- rtex->surface.u.legacy.tiling_index[0] = 14;
+ tex->surface.u.legacy.tiling_index[0] = 14;
break;
case RADEON_MICRO_MODE_ROTATED:
- rtex->surface.u.legacy.tiling_index[0] = 28;
+ tex->surface.u.legacy.tiling_index[0] = 28;
break;
default: /* depth, thick */
assert(!"unexpected micro mode");
return;
}
- } else { /* SI */
- switch (rtex->last_msaa_resolve_target_micro_mode) {
+ } else { /* GFX6 */
+ switch (tex->last_msaa_resolve_target_micro_mode) {
case RADEON_MICRO_MODE_DISPLAY:
- switch (rtex->surface.bpe) {
+ switch (tex->surface.bpe) {
case 1:
- rtex->surface.u.legacy.tiling_index[0] = 10;
+ tex->surface.u.legacy.tiling_index[0] = 10;
break;
case 2:
- rtex->surface.u.legacy.tiling_index[0] = 11;
+ tex->surface.u.legacy.tiling_index[0] = 11;
break;
default: /* 4, 8 */
- rtex->surface.u.legacy.tiling_index[0] = 12;
+ tex->surface.u.legacy.tiling_index[0] = 12;
break;
}
break;
case RADEON_MICRO_MODE_THIN:
- switch (rtex->surface.bpe) {
+ switch (tex->surface.bpe) {
case 1:
- rtex->surface.u.legacy.tiling_index[0] = 14;
+ tex->surface.u.legacy.tiling_index[0] = 14;
break;
case 2:
- rtex->surface.u.legacy.tiling_index[0] = 15;
+ tex->surface.u.legacy.tiling_index[0] = 15;
break;
case 4:
- rtex->surface.u.legacy.tiling_index[0] = 16;
+ tex->surface.u.legacy.tiling_index[0] = 16;
break;
default: /* 8, 16 */
- rtex->surface.u.legacy.tiling_index[0] = 17;
+ tex->surface.u.legacy.tiling_index[0] = 17;
break;
}
break;
}
}
- rtex->surface.micro_tile_mode = rtex->last_msaa_resolve_target_micro_mode;
+ tex->surface.micro_tile_mode = tex->last_msaa_resolve_target_micro_mode;
p_atomic_inc(&sscreen->dirty_tex_counter);
}
return;
for (i = 0; i < fb->nr_cbufs; i++) {
- struct r600_texture *tex;
+ struct si_texture *tex;
unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
if (!fb->cbufs[i])
if (level > 0)
continue;
- tex = (struct r600_texture *)fb->cbufs[i]->texture;
+ tex = (struct si_texture *)fb->cbufs[i]->texture;
/* TODO: GFX9: Implement DCC fast clear for level 0 of
* mipmapped textures. Mipmapped DCC has to clear a rectangular
!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
continue;
- /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
- if (sctx->chip_class == CIK &&
+ if (sctx->chip_class <= GFX8 &&
tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
- sctx->screen->info.drm_major == 2 &&
- sctx->screen->info.drm_minor < 38) {
+ !sctx->screen->info.htile_cmask_support_1d_tiling)
continue;
- }
+
+ /* Use a slow clear for small surfaces where the cost of
+ * the eliminate pass can be higher than the benefit of fast
+ * clear. The closed driver does this, but the numbers may differ.
+ *
+ * This helps on both dGPUs and APUs, even small APUs like Mullins.
+ */
+ bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
+ tex->buffer.b.b.width0 *
+ tex->buffer.b.b.height0 <= 512 * 512;
+ bool eliminate_needed = false;
+ bool fmask_decompress_needed = false;
/* Fast clear is the most appropriate place to enable DCC for
* displayable surfaces.
*/
- if (sctx->chip_class >= VI &&
- !(sctx->screen->debug_flags & DBG(NO_DCC_FB))) {
+ if (sctx->family == CHIP_STONEY && !too_small) {
vi_separate_dcc_try_enable(sctx, tex);
/* RB+ isn't supported with a CMASK clear only on Stoney,
* clears, which is weighed when determining whether to
* enable separate DCC.
*/
- if (tex->dcc_gather_statistics &&
- sctx->family == CHIP_STONEY)
+ if (tex->dcc_gather_statistics) /* only for Stoney */
tex->num_slow_clears++;
}
- bool need_decompress_pass = false;
-
- /* Use a slow clear for small surfaces where the cost of
- * the eliminate pass can be higher than the benefit of fast
- * clear. The closed driver does this, but the numbers may differ.
- *
- * This helps on both dGPUs and APUs, even small APUs like Mullins.
- */
- bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
- tex->buffer.b.b.width0 *
- tex->buffer.b.b.height0 <= 512 * 512;
-
/* Try to clear DCC first, otherwise try CMASK. */
if (vi_dcc_enabled(tex, 0)) {
uint32_t reset_value;
- bool eliminate_needed;
if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
continue;
- /* This can only occur with MSAA. */
- if (sctx->chip_class == VI &&
- !tex->surface.u.legacy.level[level].dcc_fast_clear_size)
- continue;
-
- if (!vi_get_fast_clear_parameters(tex->buffer.b.b.format,
+ if (!vi_get_fast_clear_parameters(sctx->screen,
+ tex->buffer.b.b.format,
fb->cbufs[i]->format,
color, &reset_value,
&eliminate_needed))
if (eliminate_needed && too_small)
continue;
- /* DCC fast clear with MSAA should clear CMASK to 0xC. */
- if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask.size) {
- /* TODO: This doesn't work with MSAA. */
- if (eliminate_needed)
- continue;
-
- si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
- tex->cmask.offset, tex->cmask.size,
- 0xCCCCCCCC, SI_COHERENCY_CB_META);
- need_decompress_pass = true;
- }
-
- vi_dcc_clear_level(sctx, tex, 0, reset_value);
+ /* TODO: This DCC+CMASK clear doesn't work with MSAA. */
+ if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer &&
+ eliminate_needed)
+ continue;
- if (eliminate_needed)
- need_decompress_pass = true;
+ if (!vi_dcc_clear_level(sctx, tex, 0, reset_value))
+ continue;
tex->separate_dcc_dirty = true;
+
+ /* DCC fast clear with MSAA should clear CMASK to 0xC. */
+ if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) {
+ uint32_t clear_value = 0xCCCCCCCC;
+ si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
+ tex->cmask_offset, tex->surface.cmask_size,
+ &clear_value, 4, SI_COHERENCY_CB_META, false);
+ fmask_decompress_needed = true;
+ }
} else {
if (too_small)
continue;
/* ensure CMASK is enabled */
si_alloc_separate_cmask(sctx->screen, tex);
- if (tex->cmask.size == 0) {
+ if (!tex->cmask_buffer)
continue;
- }
/* Do the fast clear. */
+ uint32_t clear_value = 0;
si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
- tex->cmask.offset, tex->cmask.size, 0,
- SI_COHERENCY_CB_META);
- need_decompress_pass = true;
+ tex->cmask_offset, tex->surface.cmask_size,
+ &clear_value, 4, SI_COHERENCY_CB_META, false);
+ eliminate_needed = true;
}
- if (need_decompress_pass &&
+ if ((eliminate_needed || fmask_decompress_needed) &&
!(tex->dirty_level_mask & (1 << level))) {
tex->dirty_level_mask |= 1 << level;
p_atomic_inc(&sctx->screen->compressed_colortex_counter);
/* We can change the micro tile mode before a full clear. */
si_set_optimal_micro_tile_mode(sctx->screen, tex);
- si_set_clear_color(tex, fb->cbufs[i]->format, color);
-
- sctx->framebuffer.dirty_cbufs |= 1 << i;
- si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
*buffers &= ~clear_bit;
+
+ /* Chips with DCC constant encoding don't need to set the clear
+ * color registers for DCC clear values 0 and 1.
+ */
+ if (sctx->screen->has_dcc_constant_encode && !eliminate_needed)
+ continue;
+
+ if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
+ sctx->framebuffer.dirty_cbufs |= 1 << i;
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
+ }
}
}
struct si_context *sctx = (struct si_context *)ctx;
struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
struct pipe_surface *zsbuf = fb->zsbuf;
- struct r600_texture *zstex =
- zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
+ struct si_texture *zstex =
+ zsbuf ? (struct si_texture*)zsbuf->texture : NULL;
if (buffers & PIPE_CLEAR_COLOR) {
si_do_fast_color_clear(sctx, &buffers, color);
/* These buffers cannot use fast clear, make sure to disable expansion. */
for (unsigned i = 0; i < fb->nr_cbufs; i++) {
- struct r600_texture *tex;
+ struct si_texture *tex;
/* If not clearing this buffer, skip. */
if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
continue;
- tex = (struct r600_texture *)fb->cbufs[i]->texture;
+ tex = (struct si_texture *)fb->cbufs[i]->texture;
if (tex->surface.fmask_size == 0)
tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
}
}
if (zstex &&
- si_htile_enabled(zstex, zsbuf->u.tex.level) &&
zsbuf->u.tex.first_layer == 0 &&
zsbuf->u.tex.last_layer == util_max_layer(&zstex->buffer.b.b, 0)) {
/* TC-compatible HTILE only supports depth clears to 0 or 1. */
if (buffers & PIPE_CLEAR_DEPTH &&
+ si_htile_enabled(zstex, zsbuf->u.tex.level, PIPE_MASK_Z) &&
(!zstex->tc_compatible_htile ||
depth == 0 || depth == 1)) {
/* Need to disable EXPCLEAR temporarily if clearing
sctx->db_depth_disable_expclear = true;
}
- zstex->depth_clear_value = depth;
- sctx->framebuffer.dirty_zsbuf = true;
- si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer); /* updates DB_DEPTH_CLEAR */
+ if (zstex->depth_clear_value != (float)depth) {
+ /* Update DB_DEPTH_CLEAR. */
+ zstex->depth_clear_value = depth;
+ sctx->framebuffer.dirty_zsbuf = true;
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
+ }
sctx->db_depth_clear = true;
si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
}
/* TC-compatible HTILE only supports stencil clears to 0. */
if (buffers & PIPE_CLEAR_STENCIL &&
+ si_htile_enabled(zstex, zsbuf->u.tex.level, PIPE_MASK_S) &&
(!zstex->tc_compatible_htile || stencil == 0)) {
stencil &= 0xff;
sctx->db_stencil_disable_expclear = true;
}
- zstex->stencil_clear_value = stencil;
- sctx->framebuffer.dirty_zsbuf = true;
- si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer); /* updates DB_STENCIL_CLEAR */
+ if (zstex->stencil_clear_value != (uint8_t)stencil) {
+ /* Update DB_STENCIL_CLEAR. */
+ zstex->stencil_clear_value = stencil;
+ sctx->framebuffer.dirty_zsbuf = true;
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
+ }
sctx->db_stencil_clear = true;
si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
}
* This hack decreases back-to-back ClearDepth performance.
*/
if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
- sctx->screen->clear_db_cache_before_clear)
+ sctx->screen->options.clear_db_cache_before_clear)
sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
}
si_blitter_begin(sctx, SI_CLEAR);
util_blitter_clear(sctx->blitter, fb->width, fb->height,
util_framebuffer_get_num_layers(fb),
- buffers, color, depth, stencil);
+ buffers, color, depth, stencil,
+ sctx->framebuffer.nr_samples > 1);
si_blitter_end(sctx);
if (sctx->db_depth_clear) {
bool render_condition_enabled)
{
struct si_context *sctx = (struct si_context *)ctx;
+ struct si_texture *sdst = (struct si_texture*)dst->texture;
+
+ if (dst->texture->nr_samples <= 1 && !sdst->dcc_offset) {
+ si_compute_clear_render_target(ctx, dst, color, dstx, dsty, width,
+ height, render_condition_enabled);
+ return;
+ }
si_blitter_begin(sctx, SI_CLEAR_SURFACE |
(render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
const void *data)
{
struct pipe_screen *screen = pipe->screen;
- struct r600_texture *rtex = (struct r600_texture*)tex;
+ struct si_texture *stex = (struct si_texture*)tex;
struct pipe_surface tmpl = {{0}};
struct pipe_surface *sf;
const struct util_format_description *desc =
if (!sf)
return;
- if (rtex->is_depth) {
+ if (stex->is_depth) {
unsigned clear;
float depth;
uint8_t stencil = 0;
clear = PIPE_CLEAR_DEPTH;
desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
- if (rtex->surface.has_stencil) {
+ if (stex->surface.has_stencil) {
clear |= PIPE_CLEAR_STENCIL;
desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
}
desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
if (screen->is_format_supported(screen, tex->format,
- tex->target, 0,
+ tex->target, 0, 0,
PIPE_BIND_RENDER_TARGET)) {
si_clear_render_target(pipe, sf, &color,
box->x, box->y,
void si_init_clear_functions(struct si_context *sctx)
{
- sctx->b.clear = si_clear;
sctx->b.clear_render_target = si_clear_render_target;
- sctx->b.clear_depth_stencil = si_clear_depth_stencil;
sctx->b.clear_texture = si_clear_texture;
+
+ if (sctx->has_graphics) {
+ sctx->b.clear = si_clear;
+ sctx->b.clear_depth_stencil = si_clear_depth_stencil;
+ }
}
projects / mesa.git / blobdiff