#include "si_pipe.h"
#include "sid.h"
-#include "util/u_format.h"
+#include "util/format/u_format.h"
#include "util/u_pack_color.h"
#include "util/u_surface.h"
return true;
}
-void vi_dcc_clear_level(struct si_context *sctx,
+bool vi_dcc_clear_level(struct si_context *sctx,
struct si_texture *tex,
unsigned level, unsigned clear_value)
{
dcc_offset = 0;
} else {
dcc_buffer = &tex->buffer.b.b;
- dcc_offset = tex->dcc_offset;
+ dcc_offset = tex->surface.dcc_offset;
}
if (sctx->chip_class >= GFX9) {
/* Mipmap level clears aren't implemented. */
- assert(tex->buffer.b.b.last_level == 0);
+ if (tex->buffer.b.b.last_level > 0)
+ return false;
+
/* 4x and 8x MSAA needs a sophisticated compute shader for
* the clear. See AMDVLK. */
- assert(tex->buffer.b.b.nr_storage_samples <= 2);
+ if (tex->buffer.b.b.nr_storage_samples >= 4)
+ return false;
+
clear_size = tex->surface.dcc_size;
} else {
unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
/* If this is 0, fast clear isn't possible. (can occur with MSAA) */
- assert(tex->surface.u.legacy.level[level].dcc_fast_clear_size);
+ if (!tex->surface.u.legacy.level[level].dcc_fast_clear_size)
+ return false;
+
/* Layered 4x and 8x MSAA DCC fast clears need to clear
* dcc_fast_clear_size bytes for each layer. A compute shader
* would be more efficient than separate per-layer clear operations.
*/
- assert(tex->buffer.b.b.nr_storage_samples <= 2 || num_layers == 1);
+ if (tex->buffer.b.b.nr_storage_samples >= 4 && num_layers > 1)
+ return false;
dcc_offset += tex->surface.u.legacy.level[level].dcc_offset;
clear_size = tex->surface.u.legacy.level[level].dcc_fast_clear_size *
si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
&clear_value, 4, SI_COHERENCY_CB_META, false);
+ return true;
}
/* Set the same micro tile mode as the destination of the last MSAA resolve.
int i;
/* This function is broken in BE, so just disable this path for now */
-#ifdef PIPE_ARCH_BIG_ENDIAN
+#if UTIL_ARCH_BIG_ENDIAN
return;
#endif
if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
continue;
- /* This can happen with mipmapping or MSAA. */
- if (sctx->chip_class == GFX8 &&
- !tex->surface.u.legacy.level[level].dcc_fast_clear_size)
- continue;
-
if (!vi_get_fast_clear_parameters(sctx->screen,
tex->buffer.b.b.format,
fb->cbufs[i]->format,
if (eliminate_needed && too_small)
continue;
+ /* TODO: This DCC+CMASK clear doesn't work with MSAA. */
+ if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer &&
+ eliminate_needed)
+ continue;
+
+ if (!vi_dcc_clear_level(sctx, tex, 0, reset_value))
+ continue;
+
+ tex->separate_dcc_dirty = true;
+ tex->displayable_dcc_dirty = true;
+
/* DCC fast clear with MSAA should clear CMASK to 0xC. */
if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) {
- /* TODO: This doesn't work with MSAA. */
- if (eliminate_needed)
- continue;
-
uint32_t clear_value = 0xCCCCCCCC;
si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
- tex->cmask_offset, tex->surface.cmask_size,
+ tex->surface.cmask_offset, tex->surface.cmask_size,
&clear_value, 4, SI_COHERENCY_CB_META, false);
fmask_decompress_needed = true;
}
-
- vi_dcc_clear_level(sctx, tex, 0, reset_value);
- tex->separate_dcc_dirty = true;
} else {
if (too_small)
continue;
/* Do the fast clear. */
uint32_t clear_value = 0;
si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
- tex->cmask_offset, tex->surface.cmask_size,
+ tex->surface.cmask_offset, tex->surface.cmask_size,
&clear_value, 4, SI_COHERENCY_CB_META, false);
eliminate_needed = true;
}
/* Chips with DCC constant encoding don't need to set the clear
* color registers for DCC clear values 0 and 1.
*/
- if (sctx->screen->has_dcc_constant_encode && !eliminate_needed)
+ if (sctx->screen->info.has_dcc_constant_encode && !eliminate_needed)
continue;
if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
si_blitter_begin(sctx, SI_CLEAR);
util_blitter_clear(sctx->blitter, fb->width, fb->height,
util_framebuffer_get_num_layers(fb),
- buffers, color, depth, stencil);
+ buffers, color, depth, stencil,
+ sctx->framebuffer.nr_samples > 1);
si_blitter_end(sctx);
if (sctx->db_depth_clear) {
struct si_context *sctx = (struct si_context *)ctx;
struct si_texture *sdst = (struct si_texture*)dst->texture;
- if (dst->texture->nr_samples <= 1 && !sdst->dcc_offset) {
+ if (dst->texture->nr_samples <= 1 && !sdst->surface.dcc_offset) {
si_compute_clear_render_target(ctx, dst, color, dstx, dsty, width,
height, render_condition_enabled);
return;
/* Depth is always present. */
clear = PIPE_CLEAR_DEPTH;
- desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
+ util_format_unpack_z_float(tex->format, &depth, data, 1);
if (stex->surface.has_stencil) {
clear |= PIPE_CLEAR_STENCIL;
- desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
+ util_format_unpack_s_8uint(tex->format,
+ &stencil, data, 1);
}
si_clear_depth_stencil(pipe, sf, clear, depth, stencil,
} else {
union pipe_color_union color;
- /* pipe_color_union requires the full vec4 representation. */
- if (util_format_is_pure_uint(tex->format))
- desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
- else if (util_format_is_pure_sint(tex->format))
- desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
- else
- desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
+ util_format_unpack_rgba(tex->format, color.ui, data, 1);
if (screen->is_format_supported(screen, tex->format,
tex->target, 0, 0,
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