radeonsi: Don't modify PA_SC_RASTER_CONFIG register value if rb_mask == 0

[mesa.git] / src / gallium / drivers / radeonsi / si_commands.c

diff --git a/src/gallium/drivers/radeonsi/si_commands.c b/src/gallium/drivers/radeonsi/si_commands.c
index 2efdedaf4993ce644ab1c03ea7c6a54cc8b94e11..04bc5b9b7fc012ea6aed030c64cb6b178251ea89 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_commands.c
+++ b/src/gallium/drivers/radeonsi/si_commands.c
@@ -34,99 +34,3 @@ void si_cmd_context_control(struct si_pm4_state *pm4)
        si_pm4_cmd_add(pm4, 0x80000000);
        si_pm4_cmd_end(pm4, false);
 }
-
-void si_cmd_draw_index_2(struct si_pm4_state *pm4, uint32_t max_size,
-                        uint64_t index_base, uint32_t index_count,
-                        uint32_t initiator, bool predicate)
-{
-       si_pm4_cmd_begin(pm4, PKT3_DRAW_INDEX_2);
-       si_pm4_cmd_add(pm4, max_size);
-       si_pm4_cmd_add(pm4, index_base);
-       si_pm4_cmd_add(pm4, (index_base >> 32UL) & 0xFF);
-       si_pm4_cmd_add(pm4, index_count);
-       si_pm4_cmd_add(pm4, initiator);
-       si_pm4_cmd_end(pm4, predicate);
-}
-
-void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count,
-                           uint32_t initiator, bool predicate)
-{
-       si_pm4_cmd_begin(pm4, PKT3_DRAW_INDEX_AUTO);
-       si_pm4_cmd_add(pm4, count);
-       si_pm4_cmd_add(pm4, initiator);
-       si_pm4_cmd_end(pm4, predicate);
-}
-
-void si_cmd_draw_indirect(struct si_pm4_state *pm4, uint64_t indirect_va,
-                         uint32_t indirect_offset, uint32_t base_vtx_loc,
-                         uint32_t start_inst_loc, bool predicate)
-{
-       assert(indirect_va % 8 == 0);
-       assert(indirect_offset % 4 == 0);
-
-       si_pm4_cmd_begin(pm4, PKT3_SET_BASE);
-       si_pm4_cmd_add(pm4, 1);
-       si_pm4_cmd_add(pm4, indirect_va);
-       si_pm4_cmd_add(pm4, indirect_va >> 32);
-       si_pm4_cmd_end(pm4, predicate);
-
-       si_pm4_cmd_begin(pm4, PKT3_DRAW_INDIRECT);
-       si_pm4_cmd_add(pm4, indirect_offset);
-       si_pm4_cmd_add(pm4, (base_vtx_loc - SI_SH_REG_OFFSET) >> 2);
-       si_pm4_cmd_add(pm4, (start_inst_loc - SI_SH_REG_OFFSET) >> 2);
-       si_pm4_cmd_add(pm4, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
-       si_pm4_cmd_end(pm4, predicate);
-}
-
-void si_cmd_draw_index_indirect(struct si_pm4_state *pm4, uint64_t indirect_va,
-                               uint64_t index_va, uint32_t index_max_size,
-                               uint32_t indirect_offset, uint32_t base_vtx_loc,
-                               uint32_t start_inst_loc, bool predicate)
-{
-       assert(indirect_va % 8 == 0);
-       assert(index_va % 2 == 0);
-       assert(indirect_offset % 4 == 0);
-
-       si_pm4_cmd_begin(pm4, PKT3_SET_BASE);
-       si_pm4_cmd_add(pm4, 1);
-       si_pm4_cmd_add(pm4, indirect_va);
-       si_pm4_cmd_add(pm4, indirect_va >> 32);
-       si_pm4_cmd_end(pm4, predicate);
-
-       si_pm4_cmd_begin(pm4, PKT3_INDEX_BASE);
-       si_pm4_cmd_add(pm4, index_va);
-       si_pm4_cmd_add(pm4, index_va >> 32);
-       si_pm4_cmd_end(pm4, predicate);
-
-       si_pm4_cmd_begin(pm4, PKT3_INDEX_BUFFER_SIZE);
-       si_pm4_cmd_add(pm4, index_max_size);
-       si_pm4_cmd_end(pm4, predicate);
-
-       si_pm4_cmd_begin(pm4, PKT3_DRAW_INDEX_INDIRECT);
-       si_pm4_cmd_add(pm4, indirect_offset);
-       si_pm4_cmd_add(pm4, (base_vtx_loc - SI_SH_REG_OFFSET) >> 2);
-       si_pm4_cmd_add(pm4, (start_inst_loc - SI_SH_REG_OFFSET) >> 2);
-       si_pm4_cmd_add(pm4, V_0287F0_DI_SRC_SEL_DMA);
-       si_pm4_cmd_end(pm4, predicate);
-}
-
-void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl)
-{
-       if (pm4->chip_class >= CIK) {
-               si_pm4_cmd_begin(pm4, PKT3_ACQUIRE_MEM);
-               si_pm4_cmd_add(pm4, cp_coher_cntl);     /* CP_COHER_CNTL */
-               si_pm4_cmd_add(pm4, 0xffffffff);        /* CP_COHER_SIZE */
-               si_pm4_cmd_add(pm4, 0xff);              /* CP_COHER_SIZE_HI */
-               si_pm4_cmd_add(pm4, 0);                 /* CP_COHER_BASE */
-               si_pm4_cmd_add(pm4, 0);                 /* CP_COHER_BASE_HI */
-               si_pm4_cmd_add(pm4, 0x0000000A);        /* POLL_INTERVAL */
-               si_pm4_cmd_end(pm4, false);
-       } else {
-               si_pm4_cmd_begin(pm4, PKT3_SURFACE_SYNC);
-               si_pm4_cmd_add(pm4, cp_coher_cntl);     /* CP_COHER_CNTL */
-               si_pm4_cmd_add(pm4, 0xffffffff);        /* CP_COHER_SIZE */
-               si_pm4_cmd_add(pm4, 0);                 /* CP_COHER_BASE */
-               si_pm4_cmd_add(pm4, 0x0000000A);        /* POLL_INTERVAL */
-               si_pm4_cmd_end(pm4, false);
-       }
-}