winsys/radeon: fold cs_set_flush_callback into cs_create

[mesa.git] / src / gallium / drivers / radeonsi / si_commands.c

diff --git a/src/gallium/drivers/radeonsi/si_commands.c b/src/gallium/drivers/radeonsi/si_commands.c
index e9492b8e81ec1a3cf1977f98eb584d1d9ec07225..5ddc40e1ec049f6f269a100a527bac5487e72916 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_commands.c
+++ b/src/gallium/drivers/radeonsi/si_commands.c
@@ -24,16 +24,56 @@
  *      Christian König <christian.koenig@amd.com>
  */
 
-#include "radeonsi_pipe.h"
-#include "radeonsi_pm4.h"
 #include "sid.h"
+#include "si_pipe.h"
 
-void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl)
+void si_cmd_context_control(struct si_pm4_state *pm4)
 {
-       si_pm4_cmd_begin(pm4, PKT3_SURFACE_SYNC);
-       si_pm4_cmd_add(pm4, cp_coher_cntl);     /* CP_COHER_CNTL */
-       si_pm4_cmd_add(pm4, 0xffffffff);        /* CP_COHER_SIZE */
-       si_pm4_cmd_add(pm4, 0);                 /* CP_COHER_BASE */
-       si_pm4_cmd_add(pm4, 0x0000000A);        /* POLL_INTERVAL */
+       si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
+       si_pm4_cmd_add(pm4, 0x80000000);
+       si_pm4_cmd_add(pm4, 0x80000000);
        si_pm4_cmd_end(pm4, false);
 }
+
+void si_cmd_draw_index_2(struct si_pm4_state *pm4, uint32_t max_size,
+                        uint64_t index_base, uint32_t index_count,
+                        uint32_t initiator, bool predicate)
+{
+       si_pm4_cmd_begin(pm4, PKT3_DRAW_INDEX_2);
+       si_pm4_cmd_add(pm4, max_size);
+       si_pm4_cmd_add(pm4, index_base);
+       si_pm4_cmd_add(pm4, (index_base >> 32UL) & 0xFF);
+       si_pm4_cmd_add(pm4, index_count);
+       si_pm4_cmd_add(pm4, initiator);
+       si_pm4_cmd_end(pm4, predicate);
+}
+
+void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count,
+                           uint32_t initiator, bool predicate)
+{
+       si_pm4_cmd_begin(pm4, PKT3_DRAW_INDEX_AUTO);
+       si_pm4_cmd_add(pm4, count);
+       si_pm4_cmd_add(pm4, initiator);
+       si_pm4_cmd_end(pm4, predicate);
+}
+
+void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl)
+{
+       if (pm4->chip_class >= CIK) {
+               si_pm4_cmd_begin(pm4, PKT3_ACQUIRE_MEM);
+               si_pm4_cmd_add(pm4, cp_coher_cntl);     /* CP_COHER_CNTL */
+               si_pm4_cmd_add(pm4, 0xffffffff);        /* CP_COHER_SIZE */
+               si_pm4_cmd_add(pm4, 0xff);              /* CP_COHER_SIZE_HI */
+               si_pm4_cmd_add(pm4, 0);                 /* CP_COHER_BASE */
+               si_pm4_cmd_add(pm4, 0);                 /* CP_COHER_BASE_HI */
+               si_pm4_cmd_add(pm4, 0x0000000A);        /* POLL_INTERVAL */
+               si_pm4_cmd_end(pm4, false);
+       } else {
+               si_pm4_cmd_begin(pm4, PKT3_SURFACE_SYNC);
+               si_pm4_cmd_add(pm4, cp_coher_cntl);     /* CP_COHER_CNTL */
+               si_pm4_cmd_add(pm4, 0xffffffff);        /* CP_COHER_SIZE */
+               si_pm4_cmd_add(pm4, 0);                 /* CP_COHER_BASE */
+               si_pm4_cmd_add(pm4, 0x0000000A);        /* POLL_INTERVAL */
+               si_pm4_cmd_end(pm4, false);
+       }
+}