* Christian König <christian.koenig@amd.com>
*/
-#include "radeonsi_pipe.h"
-#include "radeonsi_pm4.h"
#include "sid.h"
+#include "si_pipe.h"
void si_cmd_context_control(struct si_pm4_state *pm4)
{
si_pm4_cmd_end(pm4, predicate);
}
-void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl)
+void si_cmd_draw_indirect(struct si_pm4_state *pm4, uint64_t indirect_va,
+ uint32_t indirect_offset, uint32_t base_vtx_loc,
+ uint32_t start_inst_loc, bool predicate)
{
- if (pm4->chip_class >= CIK) {
- si_pm4_cmd_begin(pm4, PKT3_ACQUIRE_MEM);
- si_pm4_cmd_add(pm4, cp_coher_cntl); /* CP_COHER_CNTL */
- si_pm4_cmd_add(pm4, 0xffffffff); /* CP_COHER_SIZE */
- si_pm4_cmd_add(pm4, 0xff); /* CP_COHER_SIZE_HI */
- si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE */
- si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE_HI */
- si_pm4_cmd_add(pm4, 0x0000000A); /* POLL_INTERVAL */
- si_pm4_cmd_end(pm4, false);
- } else {
- si_pm4_cmd_begin(pm4, PKT3_SURFACE_SYNC);
- si_pm4_cmd_add(pm4, cp_coher_cntl); /* CP_COHER_CNTL */
- si_pm4_cmd_add(pm4, 0xffffffff); /* CP_COHER_SIZE */
- si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE */
- si_pm4_cmd_add(pm4, 0x0000000A); /* POLL_INTERVAL */
- si_pm4_cmd_end(pm4, false);
- }
+ assert(indirect_va % 8 == 0);
+ assert(indirect_offset % 4 == 0);
+
+ si_pm4_cmd_begin(pm4, PKT3_SET_BASE);
+ si_pm4_cmd_add(pm4, 1);
+ si_pm4_cmd_add(pm4, indirect_va);
+ si_pm4_cmd_add(pm4, indirect_va >> 32);
+ si_pm4_cmd_end(pm4, predicate);
+
+ si_pm4_cmd_begin(pm4, PKT3_DRAW_INDIRECT);
+ si_pm4_cmd_add(pm4, indirect_offset);
+ si_pm4_cmd_add(pm4, (base_vtx_loc - SI_SH_REG_OFFSET) >> 2);
+ si_pm4_cmd_add(pm4, (start_inst_loc - SI_SH_REG_OFFSET) >> 2);
+ si_pm4_cmd_add(pm4, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
+ si_pm4_cmd_end(pm4, predicate);
}
-void si_cmd_flush_and_inv_cb_meta(struct si_pm4_state *pm4)
+void si_cmd_draw_index_indirect(struct si_pm4_state *pm4, uint64_t indirect_va,
+ uint64_t index_va, uint32_t index_max_size,
+ uint32_t indirect_offset, uint32_t base_vtx_loc,
+ uint32_t start_inst_loc, bool predicate)
{
- si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
- si_pm4_cmd_add(pm4,
- EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
- EVENT_INDEX(0));
- si_pm4_cmd_end(pm4, false);
+ assert(indirect_va % 8 == 0);
+ assert(index_va % 2 == 0);
+ assert(indirect_offset % 4 == 0);
+
+ si_pm4_cmd_begin(pm4, PKT3_SET_BASE);
+ si_pm4_cmd_add(pm4, 1);
+ si_pm4_cmd_add(pm4, indirect_va);
+ si_pm4_cmd_add(pm4, indirect_va >> 32);
+ si_pm4_cmd_end(pm4, predicate);
+
+ si_pm4_cmd_begin(pm4, PKT3_INDEX_BASE);
+ si_pm4_cmd_add(pm4, index_va);
+ si_pm4_cmd_add(pm4, index_va >> 32);
+ si_pm4_cmd_end(pm4, predicate);
+
+ si_pm4_cmd_begin(pm4, PKT3_INDEX_BUFFER_SIZE);
+ si_pm4_cmd_add(pm4, index_max_size);
+ si_pm4_cmd_end(pm4, predicate);
+
+ si_pm4_cmd_begin(pm4, PKT3_DRAW_INDEX_INDIRECT);
+ si_pm4_cmd_add(pm4, indirect_offset);
+ si_pm4_cmd_add(pm4, (base_vtx_loc - SI_SH_REG_OFFSET) >> 2);
+ si_pm4_cmd_add(pm4, (start_inst_loc - SI_SH_REG_OFFSET) >> 2);
+ si_pm4_cmd_add(pm4, V_0287F0_DI_SRC_SEL_DMA);
+ si_pm4_cmd_end(pm4, predicate);
}