*
*/
+#include "tgsi/tgsi_parse.h"
#include "util/u_memory.h"
#include "radeon/r600_pipe_common.h"
#include "radeon/radeon_elf_util.h"
#define MAX_GLOBAL_BUFFERS 20
-/* XXX: Even though we don't pass the scratch buffer via user sgprs any more
- * LLVM still expects that we specify 4 USER_SGPRS so it can remain compatible
- * with older mesa. */
-#define NUM_USER_SGPRS 4
-
struct si_compute {
- struct si_context *ctx;
-
+ unsigned ir_type;
unsigned local_size;
unsigned private_size;
unsigned input_size;
struct si_shader shader;
- unsigned num_user_sgprs;
struct r600_resource *input_buffer;
struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
-
-#if HAVE_LLVM < 0x0306
- unsigned num_kernels;
- struct si_shader *kernels;
- LLVMContextRef llvm_ctx;
-#endif
};
static void init_scratch_buffer(struct si_context *sctx, struct si_compute *program)
/* Compute the scratch buffer size using the maximum number of waves.
* This way we don't need to recompute it for each kernel launch. */
- unsigned scratch_waves = 32 * sctx->screen->b.info.max_compute_units;
+ unsigned scratch_waves = 32 * sctx->screen->b.info.num_good_compute_units;
for (i = 0; i < program->shader.binary.global_symbol_count; i++) {
unsigned offset =
program->shader.binary.global_symbol_offsets[i];
unsigned scratch_bytes_needed;
- si_shader_binary_read_config(sctx->screen,
- &program->shader, offset);
- scratch_bytes_needed = program->shader.scratch_bytes_per_wave;
+ si_shader_binary_read_config(&program->shader.binary,
+ &program->shader.config, offset);
+ scratch_bytes_needed = program->shader.config.scratch_bytes_per_wave;
scratch_bytes = MAX2(scratch_bytes, scratch_bytes_needed);
}
if (scratch_bytes == 0)
return;
- program->shader.scratch_bo = (struct r600_resource*)
+ program->shader.scratch_bo =
si_resource_create_custom(sctx->b.b.screen,
PIPE_USAGE_DEFAULT,
scratch_bytes * scratch_waves);
* to the maximum bytes needed, so it can compute the stride
* correctly.
*/
- program->shader.scratch_bytes_per_wave = scratch_bytes;
+ program->shader.config.scratch_bytes_per_wave = scratch_bytes;
/* Patch the shader with the scratch buffer address. */
si_shader_apply_scratch_relocs(sctx,
const struct pipe_compute_state *cso)
{
struct si_context *sctx = (struct si_context *)ctx;
+ struct si_screen *sscreen = (struct si_screen *)ctx->screen;
struct si_compute *program = CALLOC_STRUCT(si_compute);
- const struct pipe_llvm_program_header *header;
- const char *code;
+ struct si_shader *shader = &program->shader;
- header = cso->prog;
- code = cso->prog + sizeof(struct pipe_llvm_program_header);
- program->ctx = sctx;
+ program->ir_type = cso->ir_type;
program->local_size = cso->req_local_mem;
program->private_size = cso->req_private_mem;
program->input_size = cso->req_input_mem;
-#if HAVE_LLVM < 0x0306
- {
- unsigned i;
- program->llvm_ctx = LLVMContextCreate();
- program->num_kernels = radeon_llvm_get_num_kernels(program->llvm_ctx,
- code, header->num_bytes);
- program->kernels = CALLOC(sizeof(struct si_shader),
- program->num_kernels);
- for (i = 0; i < program->num_kernels; i++) {
- LLVMModuleRef mod = radeon_llvm_get_kernel_module(program->llvm_ctx, i,
- code, header->num_bytes);
- si_compile_llvm(sctx->screen, &program->kernels[i], sctx->tm,
- mod);
- LLVMDisposeModule(mod);
+
+ if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
+ struct si_shader_selector sel;
+ bool scratch_enabled;
+
+ memset(&sel, 0, sizeof(sel));
+
+ sel.tokens = tgsi_dup_tokens(cso->prog);
+ if (!sel.tokens) {
+ return NULL;
}
- }
-#else
- radeon_elf_read(code, header->num_bytes, &program->shader.binary);
+ tgsi_scan_shader(cso->prog, &sel.info);
+ sel.type = PIPE_SHADER_COMPUTE;
+ sel.local_size = cso->req_local_mem;
- /* init_scratch_buffer patches the shader code with the scratch address,
- * so we need to call it before si_shader_binary_read() which uploads
- * the shader code to the GPU.
- */
- init_scratch_buffer(sctx, program);
- si_shader_binary_read(sctx->screen, &program->shader);
+ p_atomic_inc(&sscreen->b.num_shaders_created);
-#endif
- program->input_buffer = si_resource_create_custom(sctx->b.b.screen,
- PIPE_USAGE_IMMUTABLE, program->input_size);
+ program->shader.selector = &sel;
+
+ if (si_compile_tgsi_shader(sscreen, sctx->tm, &program->shader,
+ true, &sctx->b.debug)) {
+ FREE(sel.tokens);
+ return NULL;
+ }
+
+ scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
+
+ shader->config.rsrc2 = S_00B84C_USER_SGPR(SI_CS_NUM_USER_SGPR) |
+ S_00B84C_SCRATCH_EN(scratch_enabled) |
+ S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
+ S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
+ S_00B84C_LDS_SIZE(shader->config.lds_size);
+
+ FREE(sel.tokens);
+ } else {
+ const struct pipe_llvm_program_header *header;
+ const char *code;
+ header = cso->prog;
+ code = cso->prog + sizeof(struct pipe_llvm_program_header);
+
+ radeon_elf_read(code, header->num_bytes, &program->shader.binary);
+ /* init_scratch_buffer patches the shader code with the scratch address,
+ * so we need to call it before si_shader_binary_read() which uploads
+ * the shader code to the GPU.
+ */
+ init_scratch_buffer(sctx, program);
+ si_shader_binary_read_config(&program->shader.binary,
+ &program->shader.config, 0);
+ }
+ si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
+ TGSI_PROCESSOR_COMPUTE, stderr);
+ si_shader_binary_upload(sctx->screen, &program->shader);
+
+ if (program->input_size) {
+ program->input_buffer = si_resource_create_custom(sctx->b.b.screen,
+ PIPE_USAGE_IMMUTABLE, program->input_size);
+ }
return program;
}
}
static void si_launch_grid(
- struct pipe_context *ctx,
- const uint *block_layout, const uint *grid_layout,
- uint32_t pc, const void *input)
+ struct pipe_context *ctx, const struct pipe_grid_info *info)
{
struct si_context *sctx = (struct si_context*)ctx;
- struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
+ struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
struct si_compute *program = sctx->cs_shader_state.program;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct r600_resource *input_buffer = program->input_buffer;
uint64_t kernel_args_va;
uint64_t scratch_buffer_va = 0;
uint64_t shader_va;
- unsigned arg_user_sgpr_count = NUM_USER_SGPRS;
unsigned i;
struct si_shader *shader = &program->shader;
unsigned lds_blocks;
unsigned num_waves_for_scratch;
-#if HAVE_LLVM < 0x0306
- shader = &program->kernels[pc];
-#endif
-
-
radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0) | PKT3_SHADER_TYPE_S(1));
radeon_emit(cs, 0x80000000);
radeon_emit(cs, 0x80000000);
- sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
- SI_CONTEXT_INV_TC_L2 |
+ sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
+ SI_CONTEXT_INV_GLOBAL_L2 |
SI_CONTEXT_INV_ICACHE |
- SI_CONTEXT_INV_KCACHE |
+ SI_CONTEXT_INV_SMEM_L1 |
SI_CONTEXT_FLUSH_WITH_INV_L2 |
SI_CONTEXT_FLAG_COMPUTE;
si_emit_cache_flush(sctx, NULL);
pm4->compute_pkt = true;
-#if HAVE_LLVM >= 0x0306
/* Read the config information */
- si_shader_binary_read_config(sctx->screen, shader, pc);
-#endif
+ si_shader_binary_read_config(&shader->binary, &shader->config, info->pc);
/* Upload the kernel arguments */
/* The extra num_work_size_bytes are for work group / work item size information */
kernel_args_size = program->input_size + num_work_size_bytes + 8 /* For scratch va */;
- kernel_args = sctx->b.ws->buffer_map(input_buffer->cs_buf,
- sctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE);
+ kernel_args = sctx->b.ws->buffer_map(input_buffer->buf,
+ sctx->b.gfx.cs, PIPE_TRANSFER_WRITE);
for (i = 0; i < 3; i++) {
- kernel_args[i] = grid_layout[i];
- kernel_args[i + 3] = grid_layout[i] * block_layout[i];
- kernel_args[i + 6] = block_layout[i];
+ kernel_args[i] = info->grid[i];
+ kernel_args[i + 3] = info->grid[i] * info->block[i];
+ kernel_args[i + 6] = info->block[i];
}
num_waves_for_scratch = compute_num_waves_for_scratch(
- &sctx->screen->b.info, block_layout, grid_layout);
+ &sctx->screen->b.info, info->block, info->grid);
- memcpy(kernel_args + (num_work_size_bytes / 4), input, program->input_size);
+ memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
+ program->input_size);
- if (shader->scratch_bytes_per_wave > 0) {
+ if (shader->config.scratch_bytes_per_wave > 0) {
COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
"Total Scratch: %u bytes\n", num_waves_for_scratch,
- shader->scratch_bytes_per_wave,
- shader->scratch_bytes_per_wave *
+ shader->config.scratch_bytes_per_wave,
+ shader->config.scratch_bytes_per_wave *
num_waves_for_scratch);
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
shader->scratch_bo,
RADEON_USAGE_READWRITE,
RADEON_PRIO_SCRATCH_BUFFER);
kernel_args_va = input_buffer->gpu_address;
kernel_args_va += kernel_args_offset;
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, input_buffer,
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va);
si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 8, scratch_buffer_va);
si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 12,
S_008F04_BASE_ADDRESS_HI(scratch_buffer_va >> 32)
- | S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64));
+ | S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64));
si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
si_pm4_set_reg(pm4, R_00B818_COMPUTE_START_Z, 0);
si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
- S_00B81C_NUM_THREAD_FULL(block_layout[0]));
+ S_00B81C_NUM_THREAD_FULL(info->block[0]));
si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
- S_00B820_NUM_THREAD_FULL(block_layout[1]));
+ S_00B820_NUM_THREAD_FULL(info->block[1]));
si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
- S_00B824_NUM_THREAD_FULL(block_layout[2]));
+ S_00B824_NUM_THREAD_FULL(info->block[2]));
/* Global buffers */
for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
if (!buffer) {
continue;
}
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, buffer,
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
RADEON_USAGE_READWRITE,
RADEON_PRIO_COMPUTE_GLOBAL);
}
}
shader_va = shader->bo->gpu_address;
+ shader_va += info->pc;
-#if HAVE_LLVM >= 0x0306
- shader_va += pc;
-#endif
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, shader->bo,
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
- si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1,
- /* We always use at least 3 VGPRS, these come from
- * TIDIG_COMP_CNT.
- * XXX: The compiler should account for this.
- */
- S_00B848_VGPRS((MAX2(3, shader->num_vgprs) - 1) / 4)
- /* We always use at least 4 + arg_user_sgpr_count. The 4 extra
- * sgprs are from TGID_X_EN, TGID_Y_EN, TGID_Z_EN, TG_SIZE_EN
- * XXX: The compiler should account for this.
- */
- | S_00B848_SGPRS(((MAX2(4 + arg_user_sgpr_count,
- shader->num_sgprs)) - 1) / 8)
- | S_00B028_FLOAT_MODE(shader->float_mode))
- ;
+ si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1, shader->config.rsrc1);
- lds_blocks = shader->lds_size;
+ lds_blocks = shader->config.lds_size;
/* XXX: We are over allocating LDS. For SI, the shader reports LDS in
* blocks of 256 bytes, so if there are 4 bytes lds allocated in
* the shader and 4 bytes allocated by the state tracker, then
assert(lds_blocks <= 0xFF);
- si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2,
- S_00B84C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0)
- | S_00B84C_USER_SGPR(arg_user_sgpr_count)
- | S_00B84C_TGID_X_EN(1)
- | S_00B84C_TGID_Y_EN(1)
- | S_00B84C_TGID_Z_EN(1)
- | S_00B84C_TG_SIZE_EN(1)
- | S_00B84C_TIDIG_COMP_CNT(2)
- | S_00B84C_LDS_SIZE(lds_blocks)
- | S_00B84C_EXCP_EN(0))
- ;
+ shader->config.rsrc2 &= C_00B84C_LDS_SIZE;
+ shader->config.rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
+
+ si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2, shader->config.rsrc2);
si_pm4_set_reg(pm4, R_00B854_COMPUTE_RESOURCE_LIMITS, 0);
si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0,
num_waves_for_scratch =
MIN2(num_waves_for_scratch,
- 32 * sctx->screen->b.info.max_compute_units);
+ 32 * sctx->screen->b.info.num_good_compute_units);
si_pm4_set_reg(pm4, R_00B860_COMPUTE_TMPRING_SIZE,
/* The maximum value for WAVES is 32 * num CU.
* If you program this value incorrectly, the GPU will hang if
* COMPUTE_PGM_RSRC2.SCRATCH_EN is enabled.
*/
S_00B860_WAVES(num_waves_for_scratch)
- | S_00B860_WAVESIZE(shader->scratch_bytes_per_wave >> 10))
+ | S_00B860_WAVESIZE(shader->config.scratch_bytes_per_wave >> 10))
;
si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
- si_pm4_cmd_add(pm4, grid_layout[0]); /* Thread groups DIM_X */
- si_pm4_cmd_add(pm4, grid_layout[1]); /* Thread groups DIM_Y */
- si_pm4_cmd_add(pm4, grid_layout[2]); /* Thread gropus DIM_Z */
+ si_pm4_cmd_add(pm4, info->grid[0]); /* Thread groups DIM_X */
+ si_pm4_cmd_add(pm4, info->grid[1]); /* Thread groups DIM_Y */
+ si_pm4_cmd_add(pm4, info->grid[2]); /* Thread gropus DIM_Z */
si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
si_pm4_cmd_end(pm4, false);
si_pm4_free_state(sctx, pm4, ~0);
sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
- SI_CONTEXT_INV_TC_L1 |
- SI_CONTEXT_INV_TC_L2 |
+ SI_CONTEXT_INV_VMEM_L1 |
+ SI_CONTEXT_INV_GLOBAL_L2 |
SI_CONTEXT_INV_ICACHE |
- SI_CONTEXT_INV_KCACHE |
+ SI_CONTEXT_INV_SMEM_L1 |
SI_CONTEXT_FLAG_COMPUTE;
si_emit_cache_flush(sctx, NULL);
}
return;
}
-#if HAVE_LLVM < 0x0306
- if (program->kernels) {
- for (int i = 0; i < program->num_kernels; i++){
- if (program->kernels[i].bo){
- si_shader_destroy(&program->kernels[i]);
- }
- }
- FREE(program->kernels);
- }
-
- if (program->llvm_ctx){
- LLVMContextDispose(program->llvm_ctx);
- }
-#else
- FREE(program->shader.binary.config);
- FREE(program->shader.binary.rodata);
- FREE(program->shader.binary.global_symbol_offsets);
si_shader_destroy(&program->shader);
-#endif
-
pipe_resource_reference(
(struct pipe_resource **)&program->input_buffer, NULL);
-
FREE(program);
}
projects / mesa.git / blobdiff