freedreno/a3xx: only emit dirty consts

[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index 908826850f1a45c442637f816307e7d06ac21284..be6441817963b1b6f99391194fee59a911f0cd2c 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -81,7 +81,7 @@ static void *si_create_compute_state(
        for (i = 0; i < program->num_kernels; i++) {
                LLVMModuleRef mod = radeon_llvm_get_kernel_module(program->llvm_ctx, i,
                                                        code, header->num_bytes);
-               si_compile_llvm(sctx, &program->kernels[i], mod);
+               si_compile_llvm(sctx->screen, &program->kernels[i], mod);
                LLVMDisposeModule(mod);
        }
 
@@ -168,6 +168,7 @@ static void si_launch_grid(
                uint32_t pc, const void *input)
 {
        struct si_context *sctx = (struct si_context*)ctx;
+       struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
        struct si_compute *program = sctx->cs_shader_state.program;
        struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
        struct r600_resource *input_buffer = program->input_buffer;
@@ -184,18 +185,18 @@ static void si_launch_grid(
        unsigned lds_blocks;
        unsigned num_waves_for_scratch;
 
-       pm4->compute_pkt = true;
-       si_cmd_context_control(pm4);
+       radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0) | PKT3_SHADER_TYPE_S(1));
+       radeon_emit(cs, 0x80000000);
+       radeon_emit(cs, 0x80000000);
 
-       si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
-       si_pm4_cmd_add(pm4, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) |
-                           EVENT_INDEX(0x7) |
-                           EVENT_WRITE_INV_L2);
-       si_pm4_cmd_end(pm4, false);
+       sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
+                        R600_CONTEXT_INV_SHADER_CACHE |
+                        R600_CONTEXT_INV_CONST_CACHE |
+                        R600_CONTEXT_FLUSH_WITH_INV_L2 |
+                        R600_CONTEXT_FLAG_COMPUTE;
+       si_emit_cache_flush(&sctx->b, NULL);
 
-       si_pm4_inval_texture_cache(pm4);
-       si_pm4_inval_shader_cache(pm4);
-       si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
+       pm4->compute_pkt = true;
 
        /* Upload the kernel arguments */
 
@@ -360,14 +361,6 @@ static void si_launch_grid(
        si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
         si_pm4_cmd_end(pm4, false);
 
-       si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
-       si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(0x4)));
-       si_pm4_cmd_end(pm4, false);
-
-       si_pm4_inval_texture_cache(pm4);
-       si_pm4_inval_shader_cache(pm4);
-       si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
-
        si_pm4_emit(sctx, pm4);
 
 #if 0
@@ -378,6 +371,13 @@ static void si_launch_grid(
 #endif
 
        si_pm4_free_state(sctx, pm4, ~0);
+
+       sctx->b.flags |= R600_CONTEXT_CS_PARTIAL_FLUSH |
+                        R600_CONTEXT_INV_TEX_CACHE |
+                        R600_CONTEXT_INV_SHADER_CACHE |
+                        R600_CONTEXT_INV_CONST_CACHE |
+                        R600_CONTEXT_FLAG_COMPUTE;
+       si_emit_cache_flush(&sctx->b, NULL);
 }