winsys/radeon: fold cs_set_flush_callback into cs_create
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
index ead5862df3907efcb95a99694d0ee8edc0e7e4ba..c0637f6f7ece7a950556cb03004812f8bc669ad1 100644 (file)
@@ -169,7 +169,7 @@ static void si_launch_grid(
                                (struct pipe_resource*)kernel_args_buffer);
        kernel_args_va += kernel_args_offset;
 
-       si_pm4_add_bo(pm4, kernel_args_buffer, RADEON_USAGE_READ);
+       si_pm4_add_bo(pm4, kernel_args_buffer, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
 
        si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va);
        si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) | S_008F04_STRIDE(0));
@@ -192,7 +192,7 @@ static void si_launch_grid(
                if (!buffer) {
                        continue;
                }
-               si_pm4_add_bo(pm4, buffer, RADEON_USAGE_READWRITE);
+               si_pm4_add_bo(pm4, buffer, RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
        }
 
        /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
@@ -209,7 +209,7 @@ static void si_launch_grid(
        }
 
        shader_va = r600_resource_va(ctx->screen, (void *)shader->bo);
-       si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+       si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
        si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, (shader_va >> 8) & 0xffffffff);
        si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 
@@ -301,6 +301,12 @@ static void si_delete_compute_state(struct pipe_context *ctx, void* state){
        }
 
        if (program->kernels) {
+               for (int i = 0; i < program->num_kernels; i++){
+                       if (program->kernels[i].bo){
+                               si_pipe_shader_destroy(ctx, &program->kernels[i]);
+                       }
+               }
+               
                FREE(program->kernels);
        }