/*
* Copyright 2013 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
*/
#include "tgsi/tgsi_parse.h"
+#include "util/u_async_debug.h"
#include "util/u_memory.h"
#include "util/u_upload_mgr.h"
-#include "radeon/radeon_elf_util.h"
+#include "ac_rtld.h"
#include "amd_kernel_code_t.h"
-#include "radeon/r600_cs.h"
-#include "si_pipe.h"
-#include "sid.h"
+#include "si_build_pm4.h"
+#include "si_compute.h"
-#define MAX_GLOBAL_BUFFERS 20
-
-struct si_compute {
- unsigned ir_type;
- unsigned local_size;
- unsigned private_size;
- unsigned input_size;
- struct si_shader shader;
-
- struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
- bool use_code_object_v2;
-};
+#define COMPUTE_DBG(sscreen, fmt, args...) \
+ do { \
+ if ((sscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
+ } while (0);
struct dispatch_packet {
uint16_t header;
if (!program->use_code_object_v2) {
return NULL;
}
- return (const amd_kernel_code_t*)
- (program->shader.binary.code + symbol_offset);
+
+ struct ac_rtld_binary rtld;
+ if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
+ .info = &program->screen->info,
+ .num_parts = 1,
+ .elf_ptrs = &program->shader.binary.elf_buffer,
+ .elf_sizes = &program->shader.binary.elf_size }))
+ return NULL;
+
+ const amd_kernel_code_t *result = NULL;
+ const char *text;
+ size_t size;
+ if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
+ goto out;
+
+ if (symbol_offset + sizeof(amd_kernel_code_t) > size)
+ goto out;
+
+ result = (const amd_kernel_code_t*)(text + symbol_offset);
+
+out:
+ ac_rtld_close(&rtld);
+ return result;
}
static void code_object_to_config(const amd_kernel_code_t *code_object,
- struct si_shader_config *out_config) {
+ struct ac_shader_config *out_config) {
uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
align(code_object->workitem_private_segment_byte_size * 64, 1024);
}
-static void *si_create_compute_state(
- struct pipe_context *ctx,
- const struct pipe_compute_state *cso)
+/* Asynchronous compute shader compilation. */
+static void si_create_compute_state_async(void *job, int thread_index)
{
- struct si_context *sctx = (struct si_context *)ctx;
- struct si_screen *sscreen = (struct si_screen *)ctx->screen;
- struct si_compute *program = CALLOC_STRUCT(si_compute);
+ struct si_compute *program = (struct si_compute *)job;
struct si_shader *shader = &program->shader;
+ struct si_shader_selector sel;
+ struct ac_llvm_compiler *compiler;
+ struct pipe_debug_callback *debug = &program->compiler_ctx_state.debug;
+ struct si_screen *sscreen = program->screen;
+ assert(!debug->debug_message || debug->async);
+ assert(thread_index >= 0);
+ assert(thread_index < ARRAY_SIZE(sscreen->compiler));
+ compiler = &sscreen->compiler[thread_index];
- program->ir_type = cso->ir_type;
- program->local_size = cso->req_local_mem;
- program->private_size = cso->req_private_mem;
- program->input_size = cso->req_input_mem;
- program->use_code_object_v2 = HAVE_LLVM >= 0x0400 &&
- cso->ir_type == PIPE_SHADER_IR_NATIVE;
+ memset(&sel, 0, sizeof(sel));
+ sel.screen = sscreen;
- if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
- struct si_shader_selector sel;
- bool scratch_enabled;
+ if (program->ir_type == PIPE_SHADER_IR_TGSI) {
+ tgsi_scan_shader(program->ir.tgsi, &sel.info);
+ sel.tokens = program->ir.tgsi;
+ } else {
+ assert(program->ir_type == PIPE_SHADER_IR_NIR);
+ sel.nir = program->ir.nir;
- memset(&sel, 0, sizeof(sel));
+ si_nir_opts(sel.nir);
+ si_nir_scan_shader(sel.nir, &sel.info);
+ si_lower_nir(&sel);
+ }
- sel.tokens = tgsi_dup_tokens(cso->prog);
- if (!sel.tokens) {
- FREE(program);
- return NULL;
+ /* Store the declared LDS size into tgsi_shader_info for the shader
+ * cache to include it.
+ */
+ sel.info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
+
+ sel.type = PIPE_SHADER_COMPUTE;
+ si_get_active_slot_masks(&sel.info,
+ &program->active_const_and_shader_buffers,
+ &program->active_samplers_and_images);
+
+ program->shader.selector = &sel;
+ program->shader.is_monolithic = true;
+ program->uses_grid_size = sel.info.uses_grid_size;
+ program->uses_bindless_samplers = sel.info.uses_bindless_samplers;
+ program->uses_bindless_images = sel.info.uses_bindless_images;
+ program->reads_variable_block_size =
+ sel.info.uses_block_size &&
+ sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
+ program->num_cs_user_data_dwords =
+ sel.info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
+
+ void *ir_binary = si_get_ir_binary(&sel);
+
+ /* Try to load the shader from the shader cache. */
+ mtx_lock(&sscreen->shader_cache_mutex);
+
+ if (ir_binary &&
+ si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
+ mtx_unlock(&sscreen->shader_cache_mutex);
+
+ si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
+ si_shader_dump(sscreen, shader, debug, PIPE_SHADER_COMPUTE,
+ stderr, true);
+
+ if (!si_shader_binary_upload(sscreen, shader, 0))
+ program->shader.compilation_failed = true;
+ } else {
+ mtx_unlock(&sscreen->shader_cache_mutex);
+
+ if (!si_shader_create(sscreen, compiler, &program->shader, debug)) {
+ program->shader.compilation_failed = true;
+
+ if (program->ir_type == PIPE_SHADER_IR_TGSI)
+ FREE(program->ir.tgsi);
+ program->shader.selector = NULL;
+ return;
+ }
+
+ bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
+ unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
+ (sel.info.uses_grid_size ? 3 : 0) +
+ (program->reads_variable_block_size ? 3 : 0) +
+ program->num_cs_user_data_dwords;
+
+ shader->config.rsrc1 =
+ S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
+ S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
+ S_00B848_DX10_CLAMP(1) |
+ S_00B848_FLOAT_MODE(shader->config.float_mode);
+
+ shader->config.rsrc2 =
+ S_00B84C_USER_SGPR(user_sgprs) |
+ S_00B84C_SCRATCH_EN(scratch_enabled) |
+ S_00B84C_TGID_X_EN(sel.info.uses_block_id[0]) |
+ S_00B84C_TGID_Y_EN(sel.info.uses_block_id[1]) |
+ S_00B84C_TGID_Z_EN(sel.info.uses_block_id[2]) |
+ S_00B84C_TIDIG_COMP_CNT(sel.info.uses_thread_id[2] ? 2 :
+ sel.info.uses_thread_id[1] ? 1 : 0) |
+ S_00B84C_LDS_SIZE(shader->config.lds_size);
+
+ if (ir_binary) {
+ mtx_lock(&sscreen->shader_cache_mutex);
+ if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
+ FREE(ir_binary);
+ mtx_unlock(&sscreen->shader_cache_mutex);
}
+ }
- tgsi_scan_shader(cso->prog, &sel.info);
- sel.type = PIPE_SHADER_COMPUTE;
- sel.local_size = cso->req_local_mem;
+ if (program->ir_type == PIPE_SHADER_IR_TGSI)
+ FREE(program->ir.tgsi);
- p_atomic_inc(&sscreen->b.num_shaders_created);
+ program->shader.selector = NULL;
+}
- program->shader.selector = &sel;
+static void *si_create_compute_state(
+ struct pipe_context *ctx,
+ const struct pipe_compute_state *cso)
+{
+ struct si_context *sctx = (struct si_context *)ctx;
+ struct si_screen *sscreen = (struct si_screen *)ctx->screen;
+ struct si_compute *program = CALLOC_STRUCT(si_compute);
- if (si_shader_create(sscreen, sctx->tm, &program->shader,
- &sctx->b.debug)) {
- FREE(sel.tokens);
- FREE(program);
- return NULL;
+ pipe_reference_init(&program->reference, 1);
+ program->screen = (struct si_screen *)ctx->screen;
+ program->ir_type = cso->ir_type;
+ program->local_size = cso->req_local_mem;
+ program->private_size = cso->req_private_mem;
+ program->input_size = cso->req_input_mem;
+ program->use_code_object_v2 = cso->ir_type == PIPE_SHADER_IR_NATIVE;
+
+ if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
+ if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
+ program->ir.tgsi = tgsi_dup_tokens(cso->prog);
+ if (!program->ir.tgsi) {
+ FREE(program);
+ return NULL;
+ }
+ } else {
+ assert(cso->ir_type == PIPE_SHADER_IR_NIR);
+ program->ir.nir = (struct nir_shader *) cso->prog;
}
- scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
+ program->compiler_ctx_state.debug = sctx->debug;
+ program->compiler_ctx_state.is_debug_context = sctx->is_debug;
+ p_atomic_inc(&sscreen->num_shaders_created);
- shader->config.rsrc1 =
- S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
- S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
- S_00B848_DX10_CLAMP(1) |
- S_00B848_FLOAT_MODE(shader->config.float_mode);
-
- shader->config.rsrc2 = S_00B84C_USER_SGPR(SI_CS_NUM_USER_SGPR) |
- S_00B84C_SCRATCH_EN(scratch_enabled) |
- S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
- S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
- S_00B84C_LDS_SIZE(shader->config.lds_size);
-
- FREE(sel.tokens);
+ si_schedule_initial_compile(sctx, PIPE_SHADER_COMPUTE,
+ &program->ready,
+ &program->compiler_ctx_state,
+ program, si_create_compute_state_async);
} else {
const struct pipe_llvm_program_header *header;
const char *code;
header = cso->prog;
code = cso->prog + sizeof(struct pipe_llvm_program_header);
- radeon_elf_read(code, header->num_bytes, &program->shader.binary);
- if (program->use_code_object_v2) {
- const amd_kernel_code_t *code_object =
- si_compute_get_code_object(program, 0);
- code_object_to_config(code_object, &program->shader.config);
- } else {
- si_shader_binary_read_config(&program->shader.binary,
- &program->shader.config, 0);
+ program->shader.binary.elf_size = header->num_bytes;
+ program->shader.binary.elf_buffer = malloc(header->num_bytes);
+ if (!program->shader.binary.elf_buffer) {
+ FREE(program);
+ return NULL;
+ }
+ memcpy((void *)program->shader.binary.elf_buffer, code, header->num_bytes);
+
+ const amd_kernel_code_t *code_object =
+ si_compute_get_code_object(program, 0);
+ code_object_to_config(code_object, &program->shader.config);
+
+ si_shader_dump(sctx->screen, &program->shader, &sctx->debug,
+ PIPE_SHADER_COMPUTE, stderr, true);
+ if (!si_shader_binary_upload(sctx->screen, &program->shader, 0)) {
+ fprintf(stderr, "LLVM failed to upload shader\n");
+ free((void *)program->shader.binary.elf_buffer);
+ FREE(program);
+ return NULL;
}
- si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
- PIPE_SHADER_COMPUTE, stderr);
- si_shader_binary_upload(sctx->screen, &program->shader);
}
return program;
static void si_bind_compute_state(struct pipe_context *ctx, void *state)
{
struct si_context *sctx = (struct si_context*)ctx;
- sctx->cs_shader_state.program = (struct si_compute*)state;
+ struct si_compute *program = (struct si_compute*)state;
+
+ sctx->cs_shader_state.program = program;
+ if (!program)
+ return;
+
+ /* Wait because we need active slot usage masks. */
+ if (program->ir_type != PIPE_SHADER_IR_NATIVE)
+ util_queue_fence_wait(&program->ready);
+
+ si_set_active_descriptors(sctx,
+ SI_DESCS_FIRST_COMPUTE +
+ SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
+ program->active_const_and_shader_buffers);
+ si_set_active_descriptors(sctx,
+ SI_DESCS_FIRST_COMPUTE +
+ SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
+ program->active_samplers_and_images);
}
static void si_set_global_binding(
struct si_context *sctx = (struct si_context*)ctx;
struct si_compute *program = sctx->cs_shader_state.program;
+ assert(first + n <= MAX_GLOBAL_BUFFERS);
+
if (!resources) {
- for (i = first; i < first + n; i++) {
- pipe_resource_reference(&program->global_buffers[i], NULL);
+ for (i = 0; i < n; i++) {
+ pipe_resource_reference(&program->global_buffers[first + i], NULL);
}
return;
}
- for (i = first; i < first + n; i++) {
+ for (i = 0; i < n; i++) {
uint64_t va;
uint32_t offset;
- pipe_resource_reference(&program->global_buffers[i], resources[i]);
- va = r600_resource(resources[i])->gpu_address;
+ pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
+ va = si_resource(resources[i])->gpu_address;
offset = util_le32_to_cpu(*handles[i]);
va += offset;
va = util_cpu_to_le64(va);
}
}
-static void si_initialize_compute(struct si_context *sctx)
+void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
{
- struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
uint64_t bc_va;
- radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
- radeon_emit(cs, 0);
- radeon_emit(cs, 0);
- radeon_emit(cs, 0);
-
radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
/* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
- radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
+ radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
- if (sctx->b.chip_class >= CIK) {
+ if (sctx->chip_class >= GFX7) {
/* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
radeon_set_sh_reg_seq(cs,
R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
- radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
- S_00B864_SH1_CU_EN(0xffff));
- radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
- S_00B868_SH1_CU_EN(0xffff));
+ radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
+ S_00B858_SH1_CU_EN(0xffff));
+ radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
+ S_00B858_SH1_CU_EN(0xffff));
}
/* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
* kernel if we want to use something other than the default value,
* which is now 0x22f.
*/
- if (sctx->b.chip_class <= SI) {
+ if (sctx->chip_class <= GFX6) {
/* XXX: This should be:
* (number of compute units) * 4 * (waves per simd) - 1 */
/* Set the pointer to border colors. */
bc_va = sctx->border_color_buffer->gpu_address;
- if (sctx->b.chip_class >= CIK) {
+ if (sctx->chip_class >= GFX7) {
radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
- radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
+ radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
} else {
- if (sctx->screen->b.info.drm_major == 3 ||
- (sctx->screen->b.info.drm_major == 2 &&
- sctx->screen->b.info.drm_minor >= 48)) {
+ if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
bc_va >> 8);
}
}
-
- sctx->cs_shader_state.emitted_program = NULL;
- sctx->cs_shader_state.initialized = true;
}
static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
struct si_shader *shader,
- struct si_shader_config *config)
+ struct ac_shader_config *config)
{
uint64_t scratch_bo_size, scratch_needed;
scratch_bo_size = 0;
scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
if (scratch_bo_size < scratch_needed) {
- r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
+ si_resource_reference(&sctx->compute_scratch_buffer, NULL);
sctx->compute_scratch_buffer =
- si_resource_create_custom(&sctx->screen->b.b,
- PIPE_USAGE_DEFAULT, scratch_needed);
+ si_aligned_buffer_create(&sctx->screen->b,
+ SI_RESOURCE_FLAG_UNMAPPABLE,
+ PIPE_USAGE_DEFAULT,
+ scratch_needed, 256);
if (!sctx->compute_scratch_buffer)
return false;
if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
- si_shader_apply_scratch_relocs(sctx, shader, config, scratch_va);
-
- if (si_shader_binary_upload(sctx->screen, shader))
+ if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
return false;
- r600_resource_reference(&shader->scratch_bo,
+ si_resource_reference(&shader->scratch_bo,
sctx->compute_scratch_buffer);
}
const amd_kernel_code_t *code_object,
unsigned offset)
{
- struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
- struct si_shader_config inline_config = {0};
- struct si_shader_config *config;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
+ struct ac_shader_config inline_config = {0};
+ struct ac_shader_config *config;
uint64_t shader_va;
if (sctx->cs_shader_state.emitted_program == program &&
sctx->cs_shader_state.offset == offset)
return true;
- if (program->ir_type == PIPE_SHADER_IR_TGSI) {
+ if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
config = &shader->config;
} else {
unsigned lds_blocks;
config = &inline_config;
- if (code_object) {
- code_object_to_config(code_object, config);
- } else {
- si_shader_binary_read_config(&shader->binary, config, offset);
- }
+ code_object_to_config(code_object, config);
lds_blocks = config->lds_size;
- /* XXX: We are over allocating LDS. For SI, the shader reports
+ /* XXX: We are over allocating LDS. For GFX6, the shader reports
* LDS in blocks of 256 bytes, so if there are 4 bytes lds
* allocated in the shader and 4 bytes allocated by the state
* tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
*/
- if (sctx->b.chip_class <= SI) {
+ if (sctx->chip_class <= GFX6) {
lds_blocks += align(program->local_size, 256) >> 8;
} else {
lds_blocks += align(program->local_size, 512) >> 9;
}
+ /* TODO: use si_multiwave_lds_size_workaround */
assert(lds_blocks <= 0xFF);
config->rsrc2 &= C_00B84C_LDS_SIZE;
config->scratch_bytes_per_wave *
sctx->scratch_waves);
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
shader->scratch_bo, RADEON_USAGE_READWRITE,
RADEON_PRIO_SCRATCH_BUFFER);
}
+ /* Prefetch the compute shader to TC L2.
+ *
+ * We should also prefetch graphics shaders if a compute dispatch was
+ * the last command, and the compute shader if a draw call was the last
+ * command. However, that would add more complexity and we're likely
+ * to get a shader state change in that case anyway.
+ */
+ if (sctx->chip_class >= GFX7) {
+ cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
+ 0, program->shader.bo->b.b.width0);
+ }
+
shader_va = shader->bo->gpu_address + offset;
if (program->use_code_object_v2) {
/* Shader code is placed after the amd_kernel_code_t
shader_va += sizeof(amd_kernel_code_t);
}
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo,
RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
radeon_emit(cs, shader_va >> 8);
- radeon_emit(cs, shader_va >> 40);
+ radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
radeon_emit(cs, config->rsrc1);
const amd_kernel_code_t *code_object,
unsigned user_sgpr)
{
- struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
unsigned max_private_element_size = AMD_HSA_BITS_GET(
/* Disable address clamping */
uint32_t scratch_dword2 = 0xffffffff;
uint32_t scratch_dword3 =
- S_008F0C_ELEMENT_SIZE(max_private_element_size) |
S_008F0C_INDEX_STRIDE(3) |
S_008F0C_ADD_TID_ENABLE(1);
+ if (sctx->chip_class >= GFX9) {
+ assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
+ } else {
+ scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
- if (sctx->screen->b.chip_class < VI) {
- /* BUF_DATA_FORMAT is ignored, but it cannot be
- BUF_DATA_FORMAT_INVALID. */
- scratch_dword3 |=
- S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
+ if (sctx->chip_class < GFX8) {
+ /* BUF_DATA_FORMAT is ignored, but it cannot be
+ * BUF_DATA_FORMAT_INVALID. */
+ scratch_dword3 |=
+ S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
+ }
}
radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
uint64_t kernel_args_va)
{
struct si_compute *program = sctx->cs_shader_state.program;
- struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
static const enum amd_code_property_mask_t workgroup_count_masks [] = {
AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
struct dispatch_packet dispatch;
unsigned dispatch_offset;
- struct r600_resource *dispatch_buf = NULL;
+ struct si_resource *dispatch_buf = NULL;
uint64_t dispatch_va;
/* Upload dispatch ptr */
memset(&dispatch, 0, sizeof(dispatch));
- dispatch.workgroup_size_x = info->block[0];
- dispatch.workgroup_size_y = info->block[1];
- dispatch.workgroup_size_z = info->block[2];
+ dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
+ dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
+ dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
- dispatch.grid_size_x = info->grid[0] * info->block[0];
- dispatch.grid_size_y = info->grid[1] * info->block[1];
- dispatch.grid_size_z = info->grid[2] * info->block[2];
+ dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
+ dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
+ dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
- dispatch.private_segment_size = program->private_size;
- dispatch.group_segment_size = program->local_size;
+ dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
+ dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
- dispatch.kernarg_address = kernel_args_va;
+ dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
- u_upload_data(sctx->b.uploader, 0, sizeof(dispatch), 256,
- &dispatch, &dispatch_offset,
- (struct pipe_resource**)&dispatch_buf);
+ u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch),
+ 256, &dispatch, &dispatch_offset,
+ (struct pipe_resource**)&dispatch_buf);
if (!dispatch_buf) {
fprintf(stderr, "Error: Failed to allocate dispatch "
"packet.");
}
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, dispatch_buf,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf,
RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
S_008F04_STRIDE(0));
- r600_resource_reference(&dispatch_buf, NULL);
+ si_resource_reference(&dispatch_buf, NULL);
user_sgpr += 2;
}
}
}
-static void si_upload_compute_input(struct si_context *sctx,
+static bool si_upload_compute_input(struct si_context *sctx,
const amd_kernel_code_t *code_object,
const struct pipe_grid_info *info)
{
- struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
struct si_compute *program = sctx->cs_shader_state.program;
- struct r600_resource *input_buffer = NULL;
+ struct si_resource *input_buffer = NULL;
unsigned kernel_args_size;
unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
uint32_t kernel_args_offset = 0;
/* The extra num_work_size_bytes are for work group / work item size information */
kernel_args_size = program->input_size + num_work_size_bytes;
- u_upload_alloc(sctx->b.uploader, 0, kernel_args_size, 256,
+ u_upload_alloc(sctx->b.const_uploader, 0, kernel_args_size,
+ sctx->screen->info.tcc_cache_line_size,
&kernel_args_offset,
(struct pipe_resource**)&input_buffer, &kernel_args_ptr);
+ if (unlikely(!kernel_args_ptr))
+ return false;
+
kernel_args = (uint32_t*)kernel_args_ptr;
kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
if (!code_object) {
for (i = 0; i < 3; i++) {
- kernel_args[i] = info->grid[i];
- kernel_args[i + 3] = info->grid[i] * info->block[i];
- kernel_args[i + 6] = info->block[i];
+ kernel_args[i] = util_cpu_to_le32(info->grid[i]);
+ kernel_args[i + 3] = util_cpu_to_le32(info->grid[i] * info->block[i]);
+ kernel_args[i + 6] = util_cpu_to_le32(info->block[i]);
}
}
}
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer,
RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
if (code_object) {
S_008F04_STRIDE(0));
}
- r600_resource_reference(&input_buffer, NULL);
+ si_resource_reference(&input_buffer, NULL);
+
+ return true;
}
-static void si_setup_tgsi_grid(struct si_context *sctx,
+static void si_setup_tgsi_user_data(struct si_context *sctx,
const struct pipe_grid_info *info)
{
- struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+ struct si_compute *program = sctx->cs_shader_state.program;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
- 4 * SI_SGPR_GRID_SIZE;
+ 4 * SI_NUM_RESOURCE_SGPRS;
+ unsigned block_size_reg = grid_size_reg +
+ /* 12 bytes = 3 dwords. */
+ 12 * program->uses_grid_size;
+ unsigned cs_user_data_reg = block_size_reg +
+ 12 * program->reads_variable_block_size;
if (info->indirect) {
- uint64_t base_va = r600_resource(info->indirect)->gpu_address;
- uint64_t va = base_va + info->indirect_offset;
- int i;
-
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
- (struct r600_resource *)info->indirect,
- RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
-
- for (i = 0; i < 3; ++i) {
- radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
- radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
- COPY_DATA_DST_SEL(COPY_DATA_REG));
- radeon_emit(cs, (va + 4 * i));
- radeon_emit(cs, (va + 4 * i) >> 32);
- radeon_emit(cs, (grid_size_reg >> 2) + i);
- radeon_emit(cs, 0);
+ if (program->uses_grid_size) {
+ for (unsigned i = 0; i < 3; ++i) {
+ si_cp_copy_data(sctx, sctx->gfx_cs,
+ COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
+ COPY_DATA_SRC_MEM, si_resource(info->indirect),
+ info->indirect_offset + 4 * i);
+ }
}
} else {
- struct si_compute *program = sctx->cs_shader_state.program;
- bool variable_group_size =
- program->shader.selector->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
-
- radeon_set_sh_reg_seq(cs, grid_size_reg, variable_group_size ? 6 : 3);
- radeon_emit(cs, info->grid[0]);
- radeon_emit(cs, info->grid[1]);
- radeon_emit(cs, info->grid[2]);
- if (variable_group_size) {
+ if (program->uses_grid_size) {
+ radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
+ radeon_emit(cs, info->grid[0]);
+ radeon_emit(cs, info->grid[1]);
+ radeon_emit(cs, info->grid[2]);
+ }
+ if (program->reads_variable_block_size) {
+ radeon_set_sh_reg_seq(cs, block_size_reg, 3);
radeon_emit(cs, info->block[0]);
radeon_emit(cs, info->block[1]);
radeon_emit(cs, info->block[2]);
}
}
+
+ if (program->num_cs_user_data_dwords) {
+ radeon_set_sh_reg_seq(cs, cs_user_data_reg, program->num_cs_user_data_dwords);
+ radeon_emit_array(cs, sctx->cs_user_data, program->num_cs_user_data_dwords);
+ }
+}
+
+unsigned si_get_compute_resource_limits(struct si_screen *sscreen,
+ unsigned waves_per_threadgroup,
+ unsigned max_waves_per_sh,
+ unsigned threadgroups_per_cu)
+{
+ unsigned compute_resource_limits =
+ S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
+
+ if (sscreen->info.chip_class >= GFX7) {
+ unsigned num_cu_per_se = sscreen->info.num_good_compute_units /
+ sscreen->info.max_se;
+
+ /* Force even distribution on all SIMDs in CU if the workgroup
+ * size is 64. This has shown some good improvements if # of CUs
+ * per SE is not a multiple of 4.
+ */
+ if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
+ compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
+
+ assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8);
+ compute_resource_limits |= S_00B854_WAVES_PER_SH(max_waves_per_sh) |
+ S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1);
+ } else {
+ /* GFX6 */
+ if (max_waves_per_sh) {
+ unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
+ compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
+ }
+ }
+ return compute_resource_limits;
}
static void si_emit_dispatch_packets(struct si_context *sctx,
const struct pipe_grid_info *info)
{
- struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
- bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
+ struct si_screen *sscreen = sctx->screen;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
+ bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
unsigned waves_per_threadgroup =
DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
- S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0));
+ si_get_compute_resource_limits(sscreen, waves_per_threadgroup,
+ sctx->cs_max_waves_per_sh, 1));
+
+ unsigned dispatch_initiator =
+ S_00B800_COMPUTE_SHADER_EN(1) |
+ S_00B800_FORCE_START_AT_000(1) |
+ /* If the KMD allows it (there is a KMD hw register for it),
+ * allow launching waves out-of-order. (same as Vulkan) */
+ S_00B800_ORDER_MODE(sctx->chip_class >= GFX7);
+
+ const uint *last_block = info->last_block;
+ bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
- radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
- radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
- radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
+
+ if (partial_block_en) {
+ unsigned partial[3];
+
+ /* If no partial_block, these should be an entire block size, not 0. */
+ partial[0] = last_block[0] ? last_block[0] : info->block[0];
+ partial[1] = last_block[1] ? last_block[1] : info->block[1];
+ partial[2] = last_block[2] ? last_block[2] : info->block[2];
+
+ radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]) |
+ S_00B81C_NUM_THREAD_PARTIAL(partial[0]));
+ radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]) |
+ S_00B820_NUM_THREAD_PARTIAL(partial[1]));
+ radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]) |
+ S_00B824_NUM_THREAD_PARTIAL(partial[2]));
+
+ dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
+ } else {
+ radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
+ radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
+ radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
+ }
if (info->indirect) {
- uint64_t base_va = r600_resource(info->indirect)->gpu_address;
+ uint64_t base_va = si_resource(info->indirect)->gpu_address;
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
- (struct r600_resource *)info->indirect,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
+ si_resource(info->indirect),
RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
PKT3_SHADER_TYPE_S(1));
radeon_emit(cs, info->indirect_offset);
- radeon_emit(cs, 1);
+ radeon_emit(cs, dispatch_initiator);
} else {
radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
PKT3_SHADER_TYPE_S(1));
radeon_emit(cs, info->grid[0]);
radeon_emit(cs, info->grid[1]);
radeon_emit(cs, info->grid[2]);
- radeon_emit(cs, 1);
+ radeon_emit(cs, dispatch_initiator);
}
}
* compute isn't used, i.e. only one compute job can run at a time.
* If async compute is possible, the threadgroup size must be limited
* to 256 threads on all queues to avoid the bug.
- * Only SI and certain CIK chips are affected.
+ * Only GFX6 and certain GFX7 chips are affected.
*/
bool cs_regalloc_hang =
- (sctx->b.chip_class == SI ||
- sctx->b.family == CHIP_BONAIRE ||
- sctx->b.family == CHIP_KABINI) &&
+ (sctx->chip_class == GFX6 ||
+ sctx->family == CHIP_BONAIRE ||
+ sctx->family == CHIP_KABINI) &&
info->block[0] * info->block[1] * info->block[2] > 256;
if (cs_regalloc_hang)
- sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
+ sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
SI_CONTEXT_CS_PARTIAL_FLUSH;
- si_decompress_compute_textures(sctx);
+ if (program->ir_type != PIPE_SHADER_IR_NATIVE &&
+ program->shader.compilation_failed)
+ return;
+
+ if (sctx->has_graphics) {
+ if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
+ si_update_fb_dirtiness_after_rendering(sctx);
+ sctx->last_num_draw_calls = sctx->num_draw_calls;
+ }
+
+ si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
+ }
/* Add buffer sizes for memory checking in need_cs_space. */
- r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
+ si_context_add_resource_size(sctx, &program->shader.bo->b.b);
/* TODO: add the scratch buffer */
if (info->indirect) {
- r600_context_add_resource_size(ctx, info->indirect);
+ si_context_add_resource_size(sctx, info->indirect);
- /* The hw doesn't read the indirect buffer via TC L2. */
- if (r600_resource(info->indirect)->TC_L2_dirty) {
- sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
- r600_resource(info->indirect)->TC_L2_dirty = false;
+ /* Indirect buffers use TC L2 on GFX9, but not older hw. */
+ if (sctx->chip_class <= GFX8 &&
+ si_resource(info->indirect)->TC_L2_dirty) {
+ sctx->flags |= SI_CONTEXT_WB_L2;
+ si_resource(info->indirect)->TC_L2_dirty = false;
}
}
- si_need_cs_space(sctx);
+ si_need_gfx_cs_space(sctx);
+
+ if (sctx->bo_list_add_all_compute_resources)
+ si_compute_resources_add_all_to_bo_list(sctx);
+
+ if (!sctx->cs_shader_state.initialized) {
+ si_emit_initial_compute_regs(sctx, sctx->gfx_cs);
- if (!sctx->cs_shader_state.initialized)
- si_initialize_compute(sctx);
+ sctx->cs_shader_state.emitted_program = NULL;
+ sctx->cs_shader_state.initialized = true;
+ }
- if (sctx->b.flags)
- si_emit_cache_flush(sctx);
+ if (sctx->flags)
+ sctx->emit_cache_flush(sctx);
if (!si_switch_compute_shader(sctx, program, &program->shader,
code_object, info->pc))
return;
si_upload_compute_shader_descriptors(sctx);
- si_emit_compute_shader_userdata(sctx);
+ si_emit_compute_shader_pointers(sctx);
- if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
- sctx->atoms.s.render_cond->emit(&sctx->b,
- sctx->atoms.s.render_cond);
- si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
+ if (sctx->has_graphics &&
+ si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
+ sctx->atoms.s.render_cond.emit(sctx);
+ si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
}
- if (program->input_size || program->ir_type == PIPE_SHADER_IR_NATIVE)
- si_upload_compute_input(sctx, code_object, info);
+ if ((program->input_size ||
+ program->ir_type == PIPE_SHADER_IR_NATIVE) &&
+ unlikely(!si_upload_compute_input(sctx, code_object, info))) {
+ return;
+ }
/* Global buffers */
for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
- struct r600_resource *buffer =
- (struct r600_resource*)program->global_buffers[i];
+ struct si_resource *buffer =
+ si_resource(program->global_buffers[i]);
if (!buffer) {
continue;
}
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
RADEON_USAGE_READWRITE,
RADEON_PRIO_COMPUTE_GLOBAL);
}
- if (program->ir_type == PIPE_SHADER_IR_TGSI)
- si_setup_tgsi_grid(sctx, info);
-
- si_ce_pre_draw_synchronization(sctx);
+ if (program->ir_type != PIPE_SHADER_IR_NATIVE)
+ si_setup_tgsi_user_data(sctx, info);
si_emit_dispatch_packets(sctx, info);
- si_ce_post_draw_synchronization(sctx);
+ if (unlikely(sctx->current_saved_cs)) {
+ si_trace_emit(sctx);
+ si_log_compute_state(sctx, sctx->log);
+ }
sctx->compute_is_busy = true;
- sctx->b.num_compute_calls++;
+ sctx->num_compute_calls++;
if (sctx->cs_shader_state.uses_scratch)
- sctx->b.num_spill_compute_calls++;
+ sctx->num_spill_compute_calls++;
if (cs_regalloc_hang)
- sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
+ sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
}
+void si_destroy_compute(struct si_compute *program)
+{
+ if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
+ util_queue_drop_job(&program->screen->shader_compiler_queue,
+ &program->ready);
+ util_queue_fence_destroy(&program->ready);
+ }
+
+ si_shader_destroy(&program->shader);
+ FREE(program);
+}
static void si_delete_compute_state(struct pipe_context *ctx, void* state){
struct si_compute *program = (struct si_compute *)state;
struct si_context *sctx = (struct si_context*)ctx;
- if (!state) {
+ if (!state)
return;
- }
if (program == sctx->cs_shader_state.program)
sctx->cs_shader_state.program = NULL;
if (program == sctx->cs_shader_state.emitted_program)
sctx->cs_shader_state.emitted_program = NULL;
- si_shader_destroy(&program->shader);
- FREE(program);
+ si_compute_reference(&program, NULL);
}
static void si_set_compute_resources(struct pipe_context * ctx_,
void si_init_compute_functions(struct si_context *sctx)
{
- sctx->b.b.create_compute_state = si_create_compute_state;
- sctx->b.b.delete_compute_state = si_delete_compute_state;
- sctx->b.b.bind_compute_state = si_bind_compute_state;
-/* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
- sctx->b.b.set_compute_resources = si_set_compute_resources;
- sctx->b.b.set_global_binding = si_set_global_binding;
- sctx->b.b.launch_grid = si_launch_grid;
+ sctx->b.create_compute_state = si_create_compute_state;
+ sctx->b.delete_compute_state = si_delete_compute_state;
+ sctx->b.bind_compute_state = si_bind_compute_state;
+ sctx->b.set_compute_resources = si_set_compute_resources;
+ sctx->b.set_global_binding = si_set_global_binding;
+ sctx->b.launch_grid = si_launch_grid;
}