struct si_thread0_section {
struct si_shader_context *ctx;
- struct lp_build_if_state if_thread0;
LLVMValueRef vgpr_result; /* a VGPR for the value on thread 0. */
LLVMValueRef saved_exec;
};
*
* It could just be s_and_saveexec_b64 s, 1.
*/
- lp_build_if(§ion->if_thread0, &ctx->gallivm,
- LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, thread_id,
- ctx->i32_0, ""));
+ ac_build_ifcc(&ctx->ac,
+ LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, thread_id,
+ ctx->i32_0, ""), 12601);
}
/* Exit a section that only executes on thread 0 and broadcast the result
LLVMBuildStore(ctx->ac.builder, *result, section->vgpr_result);
- lp_build_endif(§ion->if_thread0);
+ ac_build_endif(&ctx->ac, 12601);
/* Broadcast the result from thread 0 to all threads. */
*result = ac_build_readlane(&ctx->ac,
for (unsigned i = 0; i < 3; i++) {
index[i] = ac_build_buffer_load_format(&ctx->ac, input_indexbuf,
index[i], ctx->i32_0, 1,
- false, true);
+ 0, true);
index[i] = ac_to_integer(&ctx->ac, index[i]);
}
}
* // Just read the value that previous waves stored.
* first_is_odd = ds.ordered.add(0);
*/
- struct lp_build_if_state if_overwrite_counter;
- lp_build_if(&if_overwrite_counter, &ctx->gallivm,
- LLVMBuildOr(builder, is_first_wave,
- current_wave_resets_index, ""));
+ ac_build_ifcc(&ctx->ac,
+ LLVMBuildOr(builder, is_first_wave,
+ current_wave_resets_index, ""), 12602);
{
/* The GDS address is always 0 with ordered append. */
tmp = si_build_ds_ordered_op(ctx, "swap",
1, true, false);
LLVMBuildStore(builder, tmp, ret);
}
- lp_build_else(&if_overwrite_counter);
+ ac_build_else(&ctx->ac, 12603);
{
/* Just read the value from GDS. */
tmp = si_build_ds_ordered_op(ctx, "add",
1, true, false);
LLVMBuildStore(builder, tmp, ret);
}
- lp_build_endif(&if_overwrite_counter);
+ ac_build_endif(&ctx->ac, 12602);
prev_wave_state = LLVMBuildLoad(builder, ret, "");
/* Ignore the return value if this is the first wave. */
vs_params[param_vertex_id] = index[i];
vs_params[param_instance_id] = instance_id;
- LLVMValueRef ret = LLVMBuildCall(builder, vs, vs_params, num_vs_params, "");
+ LLVMValueRef ret = ac_build_call(&ctx->ac, vs, vs_params, num_vs_params);
for (unsigned chan = 0; chan < 4; chan++)
pos[i][chan] = LLVMBuildExtractValue(builder, ret, chan, "");
}
* previous = ds.ordered.add(num_prims_accepted) // add the primitive count
* }
*/
- struct lp_build_if_state if_first_wave;
- lp_build_if(&if_first_wave, &ctx->gallivm, is_first_wave);
+ ac_build_ifcc(&ctx->ac, is_first_wave, 12604);
{
/* The GDS address is always 0 with ordered append. */
si_build_ds_ordered_op(ctx, "swap", ordered_wave_id,
num_prims_accepted, 0, true, true);
LLVMBuildStore(builder, ctx->i32_0, tmp_store);
}
- lp_build_else(&if_first_wave);
+ ac_build_else(&ctx->ac, 12605);
{
LLVMBuildStore(builder,
si_build_ds_ordered_op(ctx, "add", ordered_wave_id,
true, true),
tmp_store);
}
- lp_build_endif(&if_first_wave);
+ ac_build_endif(&ctx->ac, 12604);
start = LLVMBuildLoad(builder, tmp_store, "");
}
* event like this.
*/
if (VERTEX_COUNTER_GDS_MODE == 2) {
- struct lp_build_if_state if_last_wave;
- lp_build_if(&if_last_wave, &ctx->gallivm,
- LLVMBuildICmp(builder, LLVMIntEQ, global_thread_id,
- last_wave_prim_id, ""));
+ ac_build_ifcc(&ctx->ac,
+ LLVMBuildICmp(builder, LLVMIntEQ, global_thread_id,
+ last_wave_prim_id, ""), 12606);
LLVMValueRef count = LLVMBuildAdd(builder, start, num_prims_accepted, "");
count = LLVMBuildMul(builder, count,
LLVMConstInt(ctx->i32, vertices_per_prim, 0), "");
- /* VI needs to disable caching, so that the CP can see the stored value.
+ /* GFX8 needs to disable caching, so that the CP can see the stored value.
* MTYPE=3 bypasses TC L2.
*/
if (ctx->screen->info.chip_class <= GFX8) {
};
LLVMValueRef rsrc = ac_build_gather_values(&ctx->ac, desc, 4);
ac_build_buffer_store_dword(&ctx->ac, rsrc, count, 1, ctx->i32_0,
- ctx->i32_0, 0, true, true, false);
+ ctx->i32_0, 0, ac_glc | ac_slc, false);
} else {
LLVMBuildStore(builder, count,
si_expand_32bit_pointer(ctx, vertex_count_addr));
}
- lp_build_endif(&if_last_wave);
+ ac_build_endif(&ctx->ac, 12606);
} else {
/* For unordered modes that increment a vertex count instead of
* primitive count, convert it into the primitive index.
/* Now we need to store the indices of accepted primitives into
* the output index buffer.
*/
- struct lp_build_if_state if_accepted;
- lp_build_if(&if_accepted, &ctx->gallivm, accepted);
+ ac_build_ifcc(&ctx->ac, accepted, 16607);
{
/* Get the number of bits set before the index of this thread. */
LLVMValueRef prim_index = ac_build_mbcnt(&ctx->ac, accepted_threadmask);
vdata = ac_build_expand_to_vec4(&ctx->ac, vdata, 3);
ac_build_buffer_store_format(&ctx->ac, output_indexbuf, vdata,
- vindex, ctx->i32_0, 3, true,
- INDEX_STORES_USE_SLC);
+ vindex, ctx->i32_0, 3,
+ ac_glc | (INDEX_STORES_USE_SLC ? ac_slc : 0));
}
- lp_build_endif(&if_accepted);
+ ac_build_endif(&ctx->ac, 16607);
LLVMBuildRetVoid(builder);
}
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
sctx->index_ring_size_per_ib * 2,
- 2 * 1024 * 1024);
+ sctx->screen->info.pte_fragment_size);
if (!sctx->index_ring)
return false;
}
/* The compute IB is always chained, but we need to call cs_check_space to add more space. */
struct radeon_cmdbuf *cs = sctx->prim_discard_compute_cs;
- bool compute_has_space = sctx->ws->cs_check_space(cs, need_compute_dw, false);
+ ASSERTED bool compute_has_space = sctx->ws->cs_check_space(cs, need_compute_dw, false);
assert(compute_has_space);
assert(si_check_ring_space(sctx, out_indexbuf_size));
return SI_PRIM_DISCARD_ENABLED;
/* This needs to be done at the beginning of IBs due to possible
* TTM buffer moves in the kernel.
+ *
+ * TODO: update for GFX10
*/
si_emit_surface_sync(sctx, cs,
S_0085F0_TC_ACTION_ENA(1) |
S_00B84C_LDS_SIZE(shader->config.lds_size));
radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
- si_get_compute_resource_limits(sctx->screen, WAVES_PER_TG,
- MAX_WAVES_PER_SH, THREADGROUPS_PER_CU));
+ ac_get_compute_resource_limits(&sctx->screen->info,
+ WAVES_PER_TG,
+ MAX_WAVES_PER_SH,
+ THREADGROUPS_PER_CU));
sctx->compute_ib_last_shader = shader;
}
projects / mesa.git / blobdiff