radeonsi: add missing initialization of registers

[mesa.git] / src / gallium / drivers / radeonsi / si_cp_dma.c

diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index 391c4f8d50b9eb318be2e092cc9544b64ccbdc11..e2fc6f30edfb5e50e07682e6fb6e272f58498831 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -284,7 +284,7 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size, uns
  * Do memcpy between buffers using CP DMA.
  * If src or dst is NULL, it means read or write GDS, respectively.
  *
- * \param user_flags   bitmask of SI_CPDMA_*
+ * \param user_flags    bitmask of SI_CPDMA_*
  */
 void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
                            struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset,
@@ -336,6 +336,17 @@ void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
       }
    }
 
+   /* TMZ handling */
+   if (unlikely(sctx->ws->ws_is_secure(sctx->ws) &&
+                !(user_flags & SI_CPDMA_SKIP_TMZ))) {
+      bool secure = src && (si_resource(src)->flags & RADEON_FLAG_ENCRYPTED);
+      assert(!secure || (!dst || (si_resource(dst)->flags & RADEON_FLAG_ENCRYPTED)));
+      if (secure != sctx->ws->cs_is_secure(sctx->gfx_cs)) {
+         si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
+         sctx->ws->cs_set_secure(sctx->gfx_cs, secure);
+      }
+   }
+
    /* Flush the caches. */
    if ((dst || src) && !(user_flags & SI_CPDMA_SKIP_GFX_SYNC)) {
       sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH |
@@ -398,8 +409,7 @@ void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf
 
 static void cik_prefetch_shader_async(struct si_context *sctx, struct si_pm4_state *state)
 {
-   struct pipe_resource *bo = &state->bo[0]->b.b;
-   assert(state->nbo == 1);
+   struct pipe_resource *bo = &state->shader->bo->b.b;
 
    cik_prefetch_TC_L2_async(sctx, bo, 0, bo->width0);
 }