if (chunk->gfx_end != chunk->gfx_begin) {
if (chunk->gfx_begin == 0) {
- if (ctx->init_config)
- ac_parse_ib(f, ctx->init_config->pm4, ctx->init_config->ndw, NULL, 0,
+ if (ctx->cs_preamble_state)
+ ac_parse_ib(f, ctx->cs_preamble_state->pm4, ctx->cs_preamble_state->ndw, NULL, 0,
"IB2: Init config", ctx->chip_class, NULL, NULL);
- if (ctx->init_config_gs_rings)
- ac_parse_ib(f, ctx->init_config_gs_rings->pm4, ctx->init_config_gs_rings->ndw, NULL, 0,
+ if (ctx->cs_preamble_gs_rings)
+ ac_parse_ib(f, ctx->cs_preamble_gs_rings->pm4, ctx->cs_preamble_gs_rings->ndw, NULL, 0,
"IB2: Init GS rings", ctx->chip_class, NULL, NULL);
}
return slot;
}
-static void si_dump_descriptors(struct si_context *sctx, enum pipe_shader_type processor,
+static void si_dump_descriptors(struct si_context *sctx, gl_shader_stage stage,
const struct si_shader_info *info, struct u_log_context *log)
{
+ enum pipe_shader_type processor = pipe_shader_type_from_mesa(stage);
struct si_descriptors *descs =
&sctx->descriptors[SI_DESCS_FIRST_SHADER + processor * SI_NUM_SHADER_DESCS];
static const char *shader_name[] = {"VS", "PS", "GS", "TCS", "TES", "CS"};
enabled_constbuf =
sctx->const_and_shader_buffers[processor].enabled_mask >> SI_NUM_SHADER_BUFFERS;
enabled_shaderbuf = sctx->const_and_shader_buffers[processor].enabled_mask &
- u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
- enabled_shaderbuf = util_bitreverse(enabled_shaderbuf) >> (32 - SI_NUM_SHADER_BUFFERS);
+ u_bit_consecutive64(0, SI_NUM_SHADER_BUFFERS);
+ enabled_shaderbuf = 0;
+ for (int i = 0; i < SI_NUM_SHADER_BUFFERS; i++) {
+ enabled_shaderbuf |=
+ (sctx->const_and_shader_buffers[processor].enabled_mask &
+ 1llu << (SI_NUM_SHADER_BUFFERS - i - 1)) << i;
+ }
enabled_samplers = sctx->samplers[processor].enabled_mask;
enabled_images = sctx->images[processor].enabled_mask;
}
- if (processor == PIPE_SHADER_VERTEX && sctx->vb_descriptors_buffer &&
+ if (stage == MESA_SHADER_VERTEX && sctx->vb_descriptors_buffer &&
sctx->vb_descriptors_gpu_list && sctx->vertex_elements) {
assert(info); /* only CS may not have an info struct */
struct si_descriptors desc = {};
if (!state->cso || !state->current)
return;
- si_dump_descriptors(sctx, state->cso->type, &state->cso->info, log);
+ si_dump_descriptors(sctx, state->cso->info.stage, &state->cso->info, log);
}
static void si_dump_compute_descriptors(struct si_context *sctx, struct u_log_context *log)
if (!sctx->cs_shader_state.program)
return;
- si_dump_descriptors(sctx, PIPE_SHADER_COMPUTE, NULL, log);
+ si_dump_descriptors(sctx, MESA_SHADER_COMPUTE, NULL, log);
}
struct si_shader_inst {
static void si_add_split_disasm(struct si_screen *screen, struct ac_rtld_binary *rtld_binary,
struct si_shader_binary *binary, uint64_t *addr, unsigned *num,
struct si_shader_inst *instructions,
- enum pipe_shader_type shader_type, unsigned wave_size)
+ gl_shader_stage stage, unsigned wave_size)
{
if (!ac_rtld_open(rtld_binary, (struct ac_rtld_open_info){
.info = &screen->info,
- .shader_type = tgsi_processor_to_shader_stage(shader_type),
+ .shader_type = stage,
.wave_size = wave_size,
.num_parts = 1,
.elf_ptrs = &binary->elf_buffer,
return;
struct si_screen *screen = shader->selector->screen;
- enum pipe_shader_type shader_type = shader->selector->type;
+ gl_shader_stage stage = shader->selector->info.stage;
uint64_t start_addr = shader->bo->gpu_address;
uint64_t end_addr = start_addr + shader->bo->b.b.width0;
unsigned i;
if (shader->prolog) {
si_add_split_disasm(screen, &rtld_binaries[0], &shader->prolog->binary, &inst_addr, &num_inst,
- instructions, shader_type, wave_size);
+ instructions, stage, wave_size);
}
if (shader->previous_stage) {
si_add_split_disasm(screen, &rtld_binaries[1], &shader->previous_stage->binary, &inst_addr,
- &num_inst, instructions, shader_type, wave_size);
+ &num_inst, instructions, stage, wave_size);
}
if (shader->prolog2) {
si_add_split_disasm(screen, &rtld_binaries[2], &shader->prolog2->binary, &inst_addr,
- &num_inst, instructions, shader_type, wave_size);
+ &num_inst, instructions, stage, wave_size);
}
si_add_split_disasm(screen, &rtld_binaries[3], &shader->binary, &inst_addr, &num_inst,
- instructions, shader_type, wave_size);
+ instructions, stage, wave_size);
if (shader->epilog) {
si_add_split_disasm(screen, &rtld_binaries[4], &shader->epilog->binary, &inst_addr, &num_inst,
- instructions, shader_type, wave_size);
+ instructions, stage, wave_size);
}
fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n",