" - Sampler",
" - Image",
};
- unsigned num_elements[] = {
- util_last_bit(info->const_buffers_declared),
- util_last_bit(info->shader_buffers_declared),
- util_last_bit(info->samplers_declared),
- util_last_bit(info->images_declared),
+ unsigned enabled_slots[] = {
+ sctx->const_buffers[processor].enabled_mask,
+ sctx->shader_buffers[processor].enabled_mask,
+ sctx->samplers[processor].views.enabled_mask,
+ sctx->images[processor].enabled_mask,
+ };
+ unsigned required_slots[] = {
+ info ? info->const_buffers_declared : 0,
+ info ? info->shader_buffers_declared : 0,
+ info ? info->samplers_declared : 0,
+ info ? info->images_declared : 0,
};
if (processor == PIPE_SHADER_VERTEX) {
+ assert(info); /* only CS may not have an info struct */
+
si_dump_descriptor_list(&sctx->vertex_buffers, shader_name[processor],
" - Vertex buffer", info->num_inputs, f);
}
for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
si_dump_descriptor_list(descs, shader_name[processor], elem_name[i],
- num_elements[i], f);
+ util_last_bit(enabled_slots[i] | required_slots[i]), f);
}
static void si_dump_gfx_descriptors(struct si_context *sctx,
si_dump_descriptors(sctx, state->cso->type, &state->cso->info, f);
}
+static void si_dump_compute_descriptors(struct si_context *sctx, FILE *f)
+{
+ if (!sctx->cs_shader_state.program ||
+ sctx->cs_shader_state.program != sctx->cs_shader_state.emitted_program)
+ return;
+
+ si_dump_descriptors(sctx, PIPE_SHADER_COMPUTE, NULL, f);
+}
+
struct si_shader_inst {
char text[160]; /* one disasm line */
unsigned offset; /* instruction offset */
si_dump_gfx_descriptors(sctx, &sctx->tes_shader, f);
si_dump_gfx_descriptors(sctx, &sctx->gs_shader, f);
si_dump_gfx_descriptors(sctx, &sctx->ps_shader, f);
+ si_dump_compute_descriptors(sctx, f);
}
if (flags & PIPE_DUMP_LAST_COMMAND_BUFFER) {