etnaviv: native fence fd support

[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 2b911585a69ee58e88595c8c5e5836f0f6770d50..2f6f8eb57e867b63a0b137188b506f81e2ac38a4 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -404,26 +404,28 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
                va += base_level_info->offset;
        }
 
-       if (vi_dcc_enabled(tex, first_level)) {
-               meta_va = (!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
-                         tex->dcc_offset;
-
-               if (sscreen->b.chip_class <= VI)
-                       meta_va += base_level_info->dcc_offset;
-       } else if (tex->tc_compatible_htile && !is_stencil) {
-               meta_va = tex->htile_buffer->gpu_address;
-       }
-
        state[0] = va >> 8;
        state[1] &= C_008F14_BASE_ADDRESS_HI;
        state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
 
-       state[6] &= C_008F28_COMPRESSION_EN;
-       state[7] = 0;
+       if (sscreen->b.chip_class >= VI) {
+               state[6] &= C_008F28_COMPRESSION_EN;
+               state[7] = 0;
+
+               if (vi_dcc_enabled(tex, first_level)) {
+                       meta_va = (!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
+                                 tex->dcc_offset;
 
-       if (meta_va) {
-               state[6] |= S_008F28_COMPRESSION_EN(1);
-               state[7] = meta_va >> 8;
+                       if (sscreen->b.chip_class <= VI)
+                               meta_va += base_level_info->dcc_offset;
+               } else if (tex->tc_compatible_htile && !is_stencil) {
+                       meta_va = tex->htile_buffer->gpu_address;
+               }
+
+               if (meta_va) {
+                       state[6] |= S_008F28_COMPRESSION_EN(1);
+                       state[7] = meta_va >> 8;
+               }
        }
 
        if (sscreen->b.chip_class >= GFX9) {
@@ -557,6 +559,13 @@ static bool is_compressed_colortex(struct r600_texture *rtex)
               (rtex->dcc_offset && rtex->dirty_level_mask);
 }
 
+static bool depth_needs_decompression(struct r600_texture *rtex,
+                                     struct si_sampler_view *sview)
+{
+       return rtex->db_compatible &&
+              (!rtex->tc_compatible_htile || sview->is_stencil_sampler);
+}
+
 static void si_update_compressed_tex_shader_mask(struct si_context *sctx,
                                                 unsigned shader)
 {
@@ -600,8 +609,7 @@ static void si_set_sampler_views(struct pipe_context *ctx,
                                (struct r600_texture*)views[i]->texture;
                        struct si_sampler_view *rview = (struct si_sampler_view *)views[i];
 
-                       if (rtex->db_compatible &&
-                           (!rtex->tc_compatible_htile || rview->is_stencil_sampler)) {
+                       if (depth_needs_decompression(rtex, rview)) {
                                samplers->depth_texture_mask |= 1u << slot;
                        } else {
                                samplers->depth_texture_mask &= ~(1u << slot);
@@ -747,8 +755,7 @@ static void si_set_shader_image(struct si_context *ctx,
                si_make_buffer_descriptor(screen, res,
                                          view->format,
                                          view->u.buf.offset,
-                                         view->u.buf.size,
-                                         descs->list + slot * 8);
+                                         view->u.buf.size, desc);
                si_set_buf_desc_address(res, view->u.buf.offset, desc + 4);
 
                images->compressed_colortex_mask &= ~(1 << slot);
@@ -1828,8 +1835,12 @@ static void si_set_user_data_base(struct si_context *sctx,
        if (*base != new_base) {
                *base = new_base;
 
-               if (new_base)
+               if (new_base) {
                        si_mark_shader_pointers_dirty(sctx, shader);
+
+                       if (shader == PIPE_SHADER_VERTEX)
+                               sctx->last_vs_state = ~0;
+               }
        }
 }