#include "radeon/r600_cs.h"
#include "si_pipe.h"
-#include "si_shader.h"
#include "sid.h"
+#include "gfx9d.h"
#include "util/u_format.h"
-#include "util/u_math.h"
#include "util/u_memory.h"
-#include "util/u_suballoc.h"
#include "util/u_upload_mgr.h"
desc->shader_userdata_offset = shader_userdata_index * 4;
if (ce_offset) {
+ desc->uses_ce = true;
desc->ce_offset = *ce_offset;
/* make sure that ce_offset stays 32 byte aligned */
static void si_release_descriptors(struct si_descriptors *desc)
{
- pipe_resource_reference((struct pipe_resource**)&desc->buffer, NULL);
+ r600_resource_reference(&desc->buffer, NULL);
FREE(desc->list);
}
unsigned *out_offset, struct r600_resource **out_buf) {
uint64_t va;
- u_suballocator_alloc(sctx->ce_suballocator, size, 64, out_offset,
- (struct pipe_resource**)out_buf);
+ u_suballocator_alloc(sctx->ce_suballocator, size,
+ sctx->screen->b.info.tcc_cache_line_size,
+ out_offset, (struct pipe_resource**)out_buf);
if (!out_buf)
return false;
if (!desc->dirty_mask)
return true;
- if (sctx->ce_ib) {
+ if (sctx->ce_ib && desc->uses_ce) {
uint32_t const* list = (uint32_t const*)desc->list;
if (desc->ce_ram_dirty)
} else {
void *ptr;
- u_upload_alloc(sctx->b.uploader, 0, list_size, 256,
- &desc->buffer_offset,
- (struct pipe_resource**)&desc->buffer, &ptr);
+ u_upload_alloc(sctx->b.b.const_uploader, 0, list_size,
+ sctx->screen->b.info.tcc_cache_line_size,
+ &desc->buffer_offset,
+ (struct pipe_resource**)&desc->buffer, &ptr);
if (!desc->buffer)
return false; /* skip the draw call */
util_memcpy_cpu_to_le32(ptr, desc->list, list_size);
+ desc->gpu_list = ptr;
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
}
- desc->pointer_dirty = true;
desc->dirty_mask = 0;
if (atom)
static void si_sampler_view_add_buffer(struct si_context *sctx,
struct pipe_resource *resource,
- enum radeon_bo_usage usage)
+ enum radeon_bo_usage usage,
+ bool is_stencil_sampler,
+ bool check_mem)
{
- struct r600_resource *rres = (struct r600_resource*)resource;
+ struct r600_resource *rres;
+ struct r600_texture *rtex;
+ enum radeon_bo_priority priority;
if (!resource)
return;
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, rres, usage,
- r600_get_sampler_view_priority(rres));
+ if (resource->target != PIPE_BUFFER) {
+ struct r600_texture *tex = (struct r600_texture*)resource;
+
+ if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil_sampler))
+ resource = &tex->flushed_depth_texture->resource.b.b;
+ }
+
+ rres = (struct r600_resource*)resource;
+ priority = r600_get_sampler_view_priority(rres);
+
+ radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
+ rres, usage, priority,
+ check_mem);
+
+ if (resource->target == PIPE_BUFFER)
+ return;
+
+ /* Now add separate DCC or HTILE. */
+ rtex = (struct r600_texture*)resource;
+ if (rtex->dcc_separate_buffer) {
+ radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
+ rtex->dcc_separate_buffer, usage,
+ RADEON_PRIO_DCC, check_mem);
+ }
+
+ if (rtex->htile_buffer &&
+ rtex->tc_compatible_htile &&
+ !is_stencil_sampler) {
+ radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
+ rtex->htile_buffer, usage,
+ RADEON_PRIO_HTILE, check_mem);
+ }
}
static void si_sampler_views_begin_new_cs(struct si_context *sctx,
/* Add buffers to the CS. */
while (mask) {
int i = u_bit_scan(&mask);
+ struct si_sampler_view *sview = (struct si_sampler_view *)views->views[i];
- si_sampler_view_add_buffer(sctx, views->views[i]->texture,
- RADEON_USAGE_READ);
+ si_sampler_view_add_buffer(sctx, sview->base.texture,
+ RADEON_USAGE_READ,
+ sview->is_stencil_sampler, false);
}
}
+/* Set buffer descriptor fields that can be changed by reallocations. */
+static void si_set_buf_desc_address(struct r600_resource *buf,
+ uint64_t offset, uint32_t *state)
+{
+ uint64_t va = buf->gpu_address + offset;
+
+ state[0] = va;
+ state[1] &= C_008F04_BASE_ADDRESS_HI;
+ state[1] |= S_008F04_BASE_ADDRESS_HI(va >> 32);
+}
+
/* Set texture descriptor fields that can be changed by reallocations.
*
* \param tex texture
* \param is_stencil select between separate Z & Stencil
* \param state descriptor to update
*/
-void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
- const struct radeon_surf_level *base_level_info,
+void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
+ struct r600_texture *tex,
+ const struct legacy_surf_level *base_level_info,
unsigned base_level, unsigned first_level,
unsigned block_width, bool is_stencil,
uint32_t *state)
{
- uint64_t va = tex->resource.gpu_address + base_level_info->offset;
- unsigned pitch = base_level_info->nblk_x * block_width;
+ uint64_t va, meta_va = 0;
- state[1] &= C_008F14_BASE_ADDRESS_HI;
- state[3] &= C_008F1C_TILING_INDEX;
- state[4] &= C_008F20_PITCH;
- state[6] &= C_008F28_COMPRESSION_EN;
+ if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil)) {
+ tex = tex->flushed_depth_texture;
+ is_stencil = false;
+ }
+
+ va = tex->resource.gpu_address;
+
+ if (sscreen->b.chip_class >= GFX9) {
+ /* Only stencil_offset needs to be added here. */
+ if (is_stencil)
+ va += tex->surface.u.gfx9.stencil_offset;
+ else
+ va += tex->surface.u.gfx9.surf_offset;
+ } else {
+ va += base_level_info->offset;
+ }
state[0] = va >> 8;
+ state[1] &= C_008F14_BASE_ADDRESS_HI;
state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
- state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level,
- is_stencil));
- state[4] |= S_008F20_PITCH(pitch - 1);
-
- if (tex->dcc_offset && tex->surface.level[first_level].dcc_enabled) {
- state[6] |= S_008F28_COMPRESSION_EN(1);
- state[7] = (tex->resource.gpu_address +
- tex->dcc_offset +
- base_level_info->dcc_offset) >> 8;
+
+ if (sscreen->b.chip_class >= VI) {
+ state[6] &= C_008F28_COMPRESSION_EN;
+ state[7] = 0;
+
+ if (vi_dcc_enabled(tex, first_level)) {
+ meta_va = (!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
+ tex->dcc_offset;
+
+ if (sscreen->b.chip_class <= VI)
+ meta_va += base_level_info->dcc_offset;
+ } else if (tex->tc_compatible_htile && !is_stencil) {
+ meta_va = tex->htile_buffer->gpu_address;
+ }
+
+ if (meta_va) {
+ state[6] |= S_008F28_COMPRESSION_EN(1);
+ state[7] = meta_va >> 8;
+ }
+ }
+
+ if (sscreen->b.chip_class >= GFX9) {
+ state[3] &= C_008F1C_SW_MODE;
+ state[4] &= C_008F20_PITCH_GFX9;
+
+ if (is_stencil) {
+ state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
+ state[4] |= S_008F20_PITCH_GFX9(tex->surface.u.gfx9.stencil.epitch);
+ } else {
+ state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode);
+ state[4] |= S_008F20_PITCH_GFX9(tex->surface.u.gfx9.surf.epitch);
+ }
+
+ state[5] &= C_008F24_META_DATA_ADDRESS &
+ C_008F24_META_PIPE_ALIGNED &
+ C_008F24_META_RB_ALIGNED;
+ if (meta_va) {
+ struct gfx9_surf_meta_flags meta;
+
+ if (tex->dcc_offset)
+ meta = tex->surface.u.gfx9.dcc;
+ else
+ meta = tex->surface.u.gfx9.htile;
+
+ state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
+ S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
+ S_008F24_META_RB_ALIGNED(meta.rb_aligned);
+ }
+ } else {
+ /* SI-CI-VI */
+ unsigned pitch = base_level_info->nblk_x * block_width;
+ unsigned index = si_tile_mode_index(tex, base_level, is_stencil);
+
+ state[3] &= C_008F1C_TILING_INDEX;
+ state[3] |= S_008F1C_TILING_INDEX(index);
+ state[4] &= C_008F20_PITCH_GFX6;
+ state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
}
}
struct si_sampler_views *views = &sctx->samplers[shader].views;
struct si_sampler_view *rview = (struct si_sampler_view*)view;
struct si_descriptors *descs = si_sampler_descriptors(sctx, shader);
+ uint32_t *desc = descs->list + slot * 16;
if (views->views[slot] == view && !disallow_early_out)
return;
if (view) {
struct r600_texture *rtex = (struct r600_texture *)view->texture;
- uint32_t *desc = descs->list + slot * 16;
+ bool is_buffer = rtex->resource.b.b.target == PIPE_BUFFER;
- si_sampler_view_add_buffer(sctx, view->texture,
- RADEON_USAGE_READ);
+ if (unlikely(!is_buffer && rview->dcc_incompatible)) {
+ if (vi_dcc_enabled(rtex, view->u.tex.first_level))
+ if (!r600_texture_disable_dcc(&sctx->b, rtex))
+ sctx->b.decompress_dcc(&sctx->b.b, rtex);
+
+ rview->dcc_incompatible = false;
+ }
+ assert(rtex); /* views with texture == NULL aren't supported */
pipe_sampler_view_reference(&views->views[slot], view);
memcpy(desc, rview->state, 8*4);
- if (view->texture && view->texture->target != PIPE_BUFFER) {
+ if (is_buffer) {
+ rtex->resource.bind_history |= PIPE_BIND_SAMPLER_VIEW;
+
+ si_set_buf_desc_address(&rtex->resource,
+ view->u.buf.offset,
+ desc + 4);
+ } else {
bool is_separate_stencil =
- rtex->is_depth && !rtex->is_flushing_texture &&
+ rtex->db_compatible &&
rview->is_stencil_sampler;
- si_set_mutable_tex_desc_fields(rtex,
+ si_set_mutable_tex_desc_fields(sctx->screen, rtex,
rview->base_level_info,
rview->base_level,
rview->base.u.tex.first_level,
desc);
}
- if (view->texture && view->texture->target != PIPE_BUFFER &&
- rtex->fmask.size) {
+ if (!is_buffer && rtex->fmask.size) {
memcpy(desc + 8,
rview->fmask_state, 8*4);
} else {
if (views->sampler_states[slot])
memcpy(desc + 12,
- views->sampler_states[slot], 4*4);
+ views->sampler_states[slot]->val, 4*4);
}
views->enabled_mask |= 1u << slot;
+
+ /* Since this can flush, it must be done after enabled_mask is
+ * updated. */
+ si_sampler_view_add_buffer(sctx, view->texture,
+ RADEON_USAGE_READ,
+ rview->is_stencil_sampler, true);
} else {
pipe_sampler_view_reference(&views->views[slot], NULL);
- memcpy(descs->list + slot*16, null_texture_descriptor, 8*4);
+ memcpy(desc, null_texture_descriptor, 8*4);
/* Only clear the lower dwords of FMASK. */
- memcpy(descs->list + slot*16 + 8, null_texture_descriptor, 4*4);
+ memcpy(desc + 8, null_texture_descriptor, 4*4);
+ /* Re-set the sampler state if we are transitioning from FMASK. */
+ if (views->sampler_states[slot])
+ memcpy(desc + 12,
+ views->sampler_states[slot]->val, 4*4);
+
views->enabled_mask &= ~(1u << slot);
}
(rtex->dcc_offset && rtex->dirty_level_mask);
}
+static bool depth_needs_decompression(struct r600_texture *rtex,
+ struct si_sampler_view *sview)
+{
+ return rtex->db_compatible &&
+ (!rtex->tc_compatible_htile || sview->is_stencil_sampler);
+}
+
+static void si_update_compressed_tex_shader_mask(struct si_context *sctx,
+ unsigned shader)
+{
+ struct si_textures_info *samplers = &sctx->samplers[shader];
+ unsigned shader_bit = 1 << shader;
+
+ if (samplers->depth_texture_mask ||
+ samplers->compressed_colortex_mask ||
+ sctx->images[shader].compressed_colortex_mask)
+ sctx->compressed_tex_shader_mask |= shader_bit;
+ else
+ sctx->compressed_tex_shader_mask &= ~shader_bit;
+}
+
static void si_set_sampler_views(struct pipe_context *ctx,
- unsigned shader, unsigned start,
+ enum pipe_shader_type shader, unsigned start,
unsigned count,
struct pipe_sampler_view **views)
{
if (views[i]->texture && views[i]->texture->target != PIPE_BUFFER) {
struct r600_texture *rtex =
(struct r600_texture*)views[i]->texture;
+ struct si_sampler_view *rview = (struct si_sampler_view *)views[i];
- if (rtex->is_depth && !rtex->is_flushing_texture) {
+ if (depth_needs_decompression(rtex, rview)) {
samplers->depth_texture_mask |= 1u << slot;
} else {
samplers->depth_texture_mask &= ~(1u << slot);
samplers->compressed_colortex_mask &= ~(1u << slot);
}
}
+
+ si_update_compressed_tex_shader_mask(sctx, shader);
}
static void
assert(view->resource);
si_sampler_view_add_buffer(sctx, view->resource,
- RADEON_USAGE_READWRITE);
+ RADEON_USAGE_READWRITE, false, false);
}
}
si_mark_image_range_valid(const struct pipe_image_view *view)
{
struct r600_resource *res = (struct r600_resource *)view->resource;
- const struct util_format_description *desc;
- unsigned stride;
assert(res && res->b.b.target == PIPE_BUFFER);
- desc = util_format_description(view->format);
- stride = desc->block.bits / 8;
-
util_range_add(&res->valid_buffer_range,
- stride * (view->u.buf.first_element),
- stride * (view->u.buf.last_element + 1));
+ view->u.buf.offset,
+ view->u.buf.offset + view->u.buf.size);
}
static void si_set_shader_image(struct si_context *ctx,
unsigned shader,
- unsigned slot, const struct pipe_image_view *view)
+ unsigned slot, const struct pipe_image_view *view,
+ bool skip_decompress)
{
struct si_screen *screen = ctx->screen;
struct si_images_info *images = &ctx->images[shader];
struct si_descriptors *descs = si_image_descriptors(ctx, shader);
struct r600_resource *res;
+ uint32_t *desc = descs->list + slot * 8;
if (!view || !view->resource) {
si_disable_shader_image(ctx, shader, slot);
if (&images->views[slot] != view)
util_copy_image_view(&images->views[slot], view);
- si_sampler_view_add_buffer(ctx, &res->b.b,
- RADEON_USAGE_READWRITE);
-
if (res->b.b.target == PIPE_BUFFER) {
if (view->access & PIPE_IMAGE_ACCESS_WRITE)
si_mark_image_range_valid(view);
si_make_buffer_descriptor(screen, res,
view->format,
- view->u.buf.first_element,
- view->u.buf.last_element,
- descs->list + slot * 8);
+ view->u.buf.offset,
+ view->u.buf.size, desc);
+ si_set_buf_desc_address(res, view->u.buf.offset, desc + 4);
+
images->compressed_colortex_mask &= ~(1 << slot);
+ res->bind_history |= PIPE_BIND_SHADER_IMAGE;
} else {
static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
struct r600_texture *tex = (struct r600_texture *)res;
unsigned level = view->u.tex.level;
unsigned width, height, depth;
- uint32_t *desc = descs->list + slot * 8;
- bool uses_dcc = tex->dcc_offset &&
- tex->surface.level[level].dcc_enabled;
+ bool uses_dcc = vi_dcc_enabled(tex, level);
assert(!tex->is_depth);
assert(tex->fmask.size == 0);
- if (uses_dcc &&
- view->access & PIPE_IMAGE_ACCESS_WRITE) {
+ if (uses_dcc && !skip_decompress &&
+ (view->access & PIPE_IMAGE_ACCESS_WRITE ||
+ !vi_dcc_formats_compatible(res->b.b.format, view->format))) {
/* If DCC can't be disabled, at least decompress it.
* The decompression is relatively cheap if the surface
* has been decompressed already.
*/
- if (r600_texture_disable_dcc(&screen->b, tex))
+ if (r600_texture_disable_dcc(&ctx->b, tex))
uses_dcc = false;
else
ctx->b.decompress_dcc(&ctx->b.b, tex);
view->u.tex.last_layer,
width, height, depth,
desc, NULL);
- si_set_mutable_tex_desc_fields(tex, &tex->surface.level[level],
+ si_set_mutable_tex_desc_fields(screen, tex,
+ &tex->surface.u.legacy.level[level],
level, level,
util_format_get_blockwidth(view->format),
false, desc);
images->enabled_mask |= 1u << slot;
descs->dirty_mask |= 1u << slot;
ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
+
+ /* Since this can flush, it must be done after enabled_mask is updated. */
+ si_sampler_view_add_buffer(ctx, &res->b.b,
+ RADEON_USAGE_READWRITE, false, true);
}
static void
-si_set_shader_images(struct pipe_context *pipe, unsigned shader,
+si_set_shader_images(struct pipe_context *pipe,
+ enum pipe_shader_type shader,
unsigned start_slot, unsigned count,
const struct pipe_image_view *views)
{
if (views) {
for (i = 0, slot = start_slot; i < count; ++i, ++slot)
- si_set_shader_image(ctx, shader, slot, &views[i]);
+ si_set_shader_image(ctx, shader, slot, &views[i], false);
} else {
for (i = 0, slot = start_slot; i < count; ++i, ++slot)
- si_set_shader_image(ctx, shader, slot, NULL);
+ si_set_shader_image(ctx, shader, slot, NULL, false);
}
+
+ si_update_compressed_tex_shader_mask(ctx, shader);
}
static void
/* SAMPLER STATES */
-static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
+static void si_bind_sampler_states(struct pipe_context *ctx,
+ enum pipe_shader_type shader,
unsigned start, unsigned count, void **states)
{
struct si_context *sctx = (struct si_context *)ctx;
sstates[i] == samplers->views.sampler_states[slot])
continue;
+#ifdef DEBUG
+ assert(sstates[i]->magic == SI_SAMPLER_STATE_MAGIC);
+#endif
samplers->views.sampler_states[slot] = sstates[i];
/* If FMASK is bound, don't overwrite it.
* The sampler state will be set after FMASK is unbound.
*/
- if (samplers->views.views[i] &&
- samplers->views.views[i]->texture &&
- samplers->views.views[i]->texture->target != PIPE_BUFFER &&
- ((struct r600_texture*)samplers->views.views[i]->texture)->fmask.size)
+ if (samplers->views.views[slot] &&
+ samplers->views.views[slot]->texture &&
+ samplers->views.views[slot]->texture->target != PIPE_BUFFER &&
+ ((struct r600_texture*)samplers->views.views[slot]->texture)->fmask.size)
continue;
memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
}
}
+static void si_get_buffer_from_descriptors(struct si_buffer_resources *buffers,
+ struct si_descriptors *descs,
+ unsigned idx, struct pipe_resource **buf,
+ unsigned *offset, unsigned *size)
+{
+ pipe_resource_reference(buf, buffers->buffers[idx]);
+ if (*buf) {
+ struct r600_resource *res = r600_resource(*buf);
+ const uint32_t *desc = descs->list + idx * 4;
+ uint64_t va;
+
+ *size = desc[2];
+
+ assert(G_008F04_STRIDE(desc[1]) == 0);
+ va = ((uint64_t)desc[1] << 32) | desc[0];
+
+ assert(va >= res->gpu_address && va + *size <= res->gpu_address + res->bo_size);
+ *offset = va - res->gpu_address;
+ }
+}
+
/* VERTEX BUFFERS */
static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
RADEON_PRIO_DESCRIPTORS);
}
-static bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
+bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
{
+ struct si_vertex_element *velems = sctx->vertex_elements;
struct si_descriptors *desc = &sctx->vertex_buffers;
- bool bound[SI_NUM_VERTEX_BUFFERS] = {};
- unsigned i, count = sctx->vertex_elements->count;
+ unsigned i, count;
+ unsigned desc_list_byte_size;
+ unsigned first_vb_use_mask;
uint64_t va;
uint32_t *ptr;
- if (!sctx->vertex_buffers_dirty)
+ if (!sctx->vertex_buffers_dirty || !velems)
return true;
- if (!count || !sctx->vertex_elements)
+
+ count = velems->count;
+
+ if (!count)
return true;
+ desc_list_byte_size = velems->desc_list_byte_size;
+ first_vb_use_mask = velems->first_vb_use_mask;
+
/* Vertex buffer descriptors are the only ones which are uploaded
* directly through a staging buffer and don't go through
* the fine-grained upload path.
*/
- u_upload_alloc(sctx->b.uploader, 0, count * 16, 256, &desc->buffer_offset,
+ u_upload_alloc(sctx->b.b.const_uploader, 0,
+ desc_list_byte_size,
+ si_optimal_tcc_alignment(sctx, desc_list_byte_size),
+ &desc->buffer_offset,
(struct pipe_resource**)&desc->buffer, (void**)&ptr);
if (!desc->buffer)
return false;
desc->buffer, RADEON_USAGE_READ,
RADEON_PRIO_DESCRIPTORS);
- assert(count <= SI_NUM_VERTEX_BUFFERS);
+ assert(count <= SI_MAX_ATTRIBS);
for (i = 0; i < count; i++) {
- struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i];
+ struct pipe_vertex_element *ve = &velems->elements[i];
struct pipe_vertex_buffer *vb;
struct r600_resource *rbuffer;
unsigned offset;
+ unsigned vbo_index = ve->vertex_buffer_index;
uint32_t *desc = &ptr[i*4];
- if (ve->vertex_buffer_index >= ARRAY_SIZE(sctx->vertex_buffer)) {
- memset(desc, 0, 16);
- continue;
- }
-
- vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
+ vb = &sctx->vertex_buffer[vbo_index];
rbuffer = (struct r600_resource*)vb->buffer;
if (!rbuffer) {
memset(desc, 0, 16);
desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
S_008F04_STRIDE(vb->stride);
- if (sctx->b.chip_class <= CIK && vb->stride)
+ if (sctx->b.chip_class != VI && vb->stride) {
/* Round up by rounding down and adding 1 */
desc[2] = (vb->buffer->width0 - offset -
- sctx->vertex_elements->format_size[i]) /
+ velems->format_size[i]) /
vb->stride + 1;
- else
+ } else {
desc[2] = vb->buffer->width0 - offset;
+ }
- desc[3] = sctx->vertex_elements->rsrc_word3[i];
+ desc[3] = velems->rsrc_word3[i];
- if (!bound[ve->vertex_buffer_index]) {
+ if (first_vb_use_mask & (1 << i)) {
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
(struct r600_resource*)vb->buffer,
RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
- bound[ve->vertex_buffer_index] = true;
}
}
* on performance (confirmed by testing). New descriptors are always
* uploaded to a fresh new buffer, so I don't think flushing the const
* cache is needed. */
- desc->pointer_dirty = true;
si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
+ if (sctx->b.chip_class >= CIK)
+ si_mark_atom_dirty(sctx, &sctx->prefetch_L2);
sctx->vertex_buffers_dirty = false;
+ sctx->vertex_buffer_pointer_dirty = true;
return true;
}
{
void *tmp;
- u_upload_alloc(sctx->b.uploader, 0, size, 256, const_offset,
+ u_upload_alloc(sctx->b.b.const_uploader, 0, size,
+ si_optimal_tcc_alignment(sctx, size),
+ const_offset,
(struct pipe_resource**)rbuffer, &tmp);
if (*rbuffer)
util_memcpy_cpu_to_le32(tmp, ptr, size);
} else {
pipe_resource_reference(&buffer, input->buffer);
va = r600_resource(buffer)->gpu_address + input->buffer_offset;
+ /* Only track usage for non-user buffers. */
+ r600_resource(buffer)->bind_history |= PIPE_BIND_CONSTANT_BUFFER;
}
/* Set the descriptor. */
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
buffers->buffers[slot] = buffer;
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
- (struct r600_resource*)buffer,
- buffers->shader_usage, buffers->priority);
+ radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
+ (struct r600_resource*)buffer,
+ buffers->shader_usage,
+ buffers->priority, true);
buffers->enabled_mask |= 1u << slot;
} else {
/* Clear the descriptor. */
}
static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
- uint shader, uint slot,
+ enum pipe_shader_type shader, uint slot,
const struct pipe_constant_buffer *input)
{
struct si_context *sctx = (struct si_context *)ctx;
slot, input);
}
+void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
+ uint slot, struct pipe_constant_buffer *cbuf)
+{
+ cbuf->user_buffer = NULL;
+ si_get_buffer_from_descriptors(
+ &sctx->const_buffers[shader],
+ si_const_buffer_descriptors(sctx, shader),
+ slot, &cbuf->buffer, &cbuf->buffer_offset, &cbuf->buffer_size);
+}
+
/* SHADER BUFFERS */
static unsigned
-si_shader_buffer_descriptors_idx(unsigned shader)
+si_shader_buffer_descriptors_idx(enum pipe_shader_type shader)
{
return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
SI_SHADER_DESCS_SHADER_BUFFERS;
}
static struct si_descriptors *
-si_shader_buffer_descriptors(struct si_context *sctx, unsigned shader)
+si_shader_buffer_descriptors(struct si_context *sctx,
+ enum pipe_shader_type shader)
{
return &sctx->descriptors[si_shader_buffer_descriptors_idx(shader)];
}
-static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
+static void si_set_shader_buffers(struct pipe_context *ctx,
+ enum pipe_shader_type shader,
unsigned start_slot, unsigned count,
const struct pipe_shader_buffer *sbuffers)
{
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buf,
- buffers->shader_usage, buffers->priority);
+ radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx, buf,
+ buffers->shader_usage,
+ buffers->priority, true);
+ buf->bind_history |= PIPE_BIND_SHADER_BUFFER;
+
buffers->enabled_mask |= 1u << slot;
descs->dirty_mask |= 1u << slot;
sctx->descriptors_dirty |=
1u << si_shader_buffer_descriptors_idx(shader);
+
+ util_range_add(&buf->valid_buffer_range, sbuffer->buffer_offset,
+ sbuffer->buffer_offset + sbuffer->buffer_size);
+ }
+}
+
+void si_get_shader_buffers(struct si_context *sctx,
+ enum pipe_shader_type shader,
+ uint start_slot, uint count,
+ struct pipe_shader_buffer *sbuf)
+{
+ struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
+ struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
+
+ for (unsigned i = 0; i < count; ++i) {
+ si_get_buffer_from_descriptors(
+ buffers, descs, start_slot + i,
+ &sbuf[i].buffer, &sbuf[i].buffer_offset,
+ &sbuf[i].buffer_size);
}
}
S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
- S_008F0C_ELEMENT_SIZE(element_size) |
S_008F0C_INDEX_STRIDE(index_stride) |
S_008F0C_ADD_TID_ENABLE(add_tid);
+ if (sctx->b.chip_class >= GFX9)
+ assert(!swizzle || element_size == 1); /* always 4 bytes on GFX9 */
+ else
+ desc[3] |= S_008F0C_ELEMENT_SIZE(element_size);
+
pipe_resource_reference(&buffers->buffers[slot], buffer);
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
(struct r600_resource*)buffer,
* and most other clients can use TC L2 as well, we don't need
* to flush it.
*
- * The only case which requires flushing it is VGT DMA index
- * fetching, which is a rare case. Thus, flag the TC L2
- * dirtiness in the resource and handle it when index fetching
- * is used.
+ * The only cases which requires flushing it is VGT DMA index
+ * fetching (on <= CIK) and indirect draw data, which are rare
+ * cases. Thus, flag the TC L2 dirtiness in the resource and
+ * handle it at draw call time.
*/
for (i = 0; i < sctx->b.streamout.num_targets; i++)
if (sctx->b.streamout.targets[i])
/* Set the resource. */
pipe_resource_reference(&buffers->buffers[bufidx],
buffer);
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
- (struct r600_resource*)buffer,
- buffers->shader_usage, buffers->priority);
+ radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
+ (struct r600_resource*)buffer,
+ buffers->shader_usage,
+ RADEON_PRIO_SHADER_RW_BUFFER,
+ true);
+ r600_resource(buffer)->bind_history |= PIPE_BIND_STREAM_OUTPUT;
+
buffers->enabled_mask |= 1u << bufidx;
} else {
/* Clear the descriptor and unset the resource. */
uint64_t offset_within_buffer = old_desc_va - old_buf_va;
/* Update the descriptor. */
- uint64_t va = r600_resource(new_buf)->gpu_address + offset_within_buffer;
-
- desc[0] = va;
- desc[1] = (desc[1] & C_008F04_BASE_ADDRESS_HI) |
- S_008F04_BASE_ADDRESS_HI(va >> 32);
+ si_set_buf_desc_address(r600_resource(new_buf), offset_within_buffer,
+ desc);
}
/* INTERNAL CONST BUFFERS */
for (int i = 0; i < SI_NUM_SHADERS; ++i) {
si_samplers_update_compressed_colortex_mask(&sctx->samplers[i]);
si_images_update_compressed_colortex_mask(&sctx->images[i]);
+ si_update_compressed_tex_shader_mask(sctx, i);
}
}
descs->dirty_mask |= 1u << i;
sctx->descriptors_dirty |= 1u << descriptors_idx;
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
- (struct r600_resource *)buf,
- buffers->shader_usage,
- buffers->priority);
+ radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
+ (struct r600_resource *)buf,
+ buffers->shader_usage,
+ buffers->priority, true);
}
}
}
{
struct si_context *sctx = (struct si_context*)ctx;
struct r600_resource *rbuffer = r600_resource(buf);
- unsigned i, shader, alignment = rbuffer->buf->alignment;
+ unsigned i, shader;
uint64_t old_va = rbuffer->gpu_address;
unsigned num_elems = sctx->vertex_elements ?
sctx->vertex_elements->count : 0;
- struct si_sampler_view *view;
/* Reallocate the buffer in the same pipe_resource. */
- r600_init_resource(&sctx->screen->b, rbuffer, rbuffer->b.b.width0,
- alignment);
+ r600_alloc_resource(&sctx->screen->b, rbuffer);
/* We changed the buffer, now we need to bind it where the old one
* was bound. This consists of 2 things:
*/
/* Vertex buffers. */
- for (i = 0; i < num_elems; i++) {
- int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
+ if (rbuffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
+ for (i = 0; i < num_elems; i++) {
+ int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
- if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
- continue;
- if (!sctx->vertex_buffer[vb].buffer)
- continue;
+ if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
+ continue;
+ if (!sctx->vertex_buffer[vb].buffer)
+ continue;
- if (sctx->vertex_buffer[vb].buffer == buf) {
- sctx->vertex_buffers_dirty = true;
- break;
+ if (sctx->vertex_buffer[vb].buffer == buf) {
+ sctx->vertex_buffers_dirty = true;
+ break;
+ }
}
}
/* Streamout buffers. (other internal buffers can't be invalidated) */
- for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
- struct si_buffer_resources *buffers = &sctx->rw_buffers;
- struct si_descriptors *descs =
- &sctx->descriptors[SI_DESCS_RW_BUFFERS];
+ if (rbuffer->bind_history & PIPE_BIND_STREAM_OUTPUT) {
+ for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
+ struct si_buffer_resources *buffers = &sctx->rw_buffers;
+ struct si_descriptors *descs =
+ &sctx->descriptors[SI_DESCS_RW_BUFFERS];
- if (buffers->buffers[i] != buf)
- continue;
-
- si_desc_reset_buffer_offset(ctx, descs->list + i*4,
- old_va, buf);
- descs->dirty_mask |= 1u << i;
- sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
+ if (buffers->buffers[i] != buf)
+ continue;
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
- rbuffer, buffers->shader_usage,
- buffers->priority);
-
- /* Update the streamout state. */
- if (sctx->b.streamout.begin_emitted)
- r600_emit_streamout_end(&sctx->b);
- sctx->b.streamout.append_bitmask =
- sctx->b.streamout.enabled_mask;
- r600_streamout_buffers_dirty(&sctx->b);
+ si_desc_reset_buffer_offset(ctx, descs->list + i*4,
+ old_va, buf);
+ descs->dirty_mask |= 1u << i;
+ sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
+
+ radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
+ rbuffer, buffers->shader_usage,
+ RADEON_PRIO_SHADER_RW_BUFFER,
+ true);
+
+ /* Update the streamout state. */
+ if (sctx->b.streamout.begin_emitted)
+ r600_emit_streamout_end(&sctx->b);
+ sctx->b.streamout.append_bitmask =
+ sctx->b.streamout.enabled_mask;
+ r600_streamout_buffers_dirty(&sctx->b);
+ }
}
/* Constant and shader buffers. */
- for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
- si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
- si_const_buffer_descriptors_idx(shader),
- buf, old_va);
- si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
- si_shader_buffer_descriptors_idx(shader),
- buf, old_va);
+ if (rbuffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
+ for (shader = 0; shader < SI_NUM_SHADERS; shader++)
+ si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
+ si_const_buffer_descriptors_idx(shader),
+ buf, old_va);
}
- /* Texture buffers - update virtual addresses in sampler view descriptors. */
- LIST_FOR_EACH_ENTRY(view, &sctx->b.texture_buffers, list) {
- if (view->base.texture == buf) {
- si_desc_reset_buffer_offset(ctx, &view->state[4], old_va, buf);
- }
+ if (rbuffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
+ for (shader = 0; shader < SI_NUM_SHADERS; shader++)
+ si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
+ si_shader_buffer_descriptors_idx(shader),
+ buf, old_va);
}
- /* Texture buffers - update bindings. */
- for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
- struct si_sampler_views *views = &sctx->samplers[shader].views;
- struct si_descriptors *descs =
- si_sampler_descriptors(sctx, shader);
- unsigned mask = views->enabled_mask;
- while (mask) {
- unsigned i = u_bit_scan(&mask);
- if (views->views[i]->texture == buf) {
- si_desc_reset_buffer_offset(ctx,
- descs->list +
- i * 16 + 4,
- old_va, buf);
- descs->dirty_mask |= 1u << i;
- sctx->descriptors_dirty |=
- 1u << si_sampler_descriptors_idx(shader);
-
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
- rbuffer, RADEON_USAGE_READ,
- RADEON_PRIO_SAMPLER_BUFFER);
+ if (rbuffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
+ /* Texture buffers - update bindings. */
+ for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
+ struct si_sampler_views *views = &sctx->samplers[shader].views;
+ struct si_descriptors *descs =
+ si_sampler_descriptors(sctx, shader);
+ unsigned mask = views->enabled_mask;
+
+ while (mask) {
+ unsigned i = u_bit_scan(&mask);
+ if (views->views[i]->texture == buf) {
+ si_desc_reset_buffer_offset(ctx,
+ descs->list +
+ i * 16 + 4,
+ old_va, buf);
+ descs->dirty_mask |= 1u << i;
+ sctx->descriptors_dirty |=
+ 1u << si_sampler_descriptors_idx(shader);
+
+ radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
+ rbuffer, RADEON_USAGE_READ,
+ RADEON_PRIO_SAMPLER_BUFFER,
+ true);
+ }
}
}
}
/* Shader images */
- for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
- struct si_images_info *images = &sctx->images[shader];
- struct si_descriptors *descs =
- si_image_descriptors(sctx, shader);
- unsigned mask = images->enabled_mask;
-
- while (mask) {
- unsigned i = u_bit_scan(&mask);
-
- if (images->views[i].resource == buf) {
- if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
- si_mark_image_range_valid(&images->views[i]);
-
- si_desc_reset_buffer_offset(
- ctx, descs->list + i * 8 + 4,
- old_va, buf);
- descs->dirty_mask |= 1u << i;
- sctx->descriptors_dirty |=
- 1u << si_image_descriptors_idx(shader);
-
- radeon_add_to_buffer_list(
- &sctx->b, &sctx->b.gfx, rbuffer,
- RADEON_USAGE_READWRITE,
- RADEON_PRIO_SAMPLER_BUFFER);
+ if (rbuffer->bind_history & PIPE_BIND_SHADER_IMAGE) {
+ for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
+ struct si_images_info *images = &sctx->images[shader];
+ struct si_descriptors *descs =
+ si_image_descriptors(sctx, shader);
+ unsigned mask = images->enabled_mask;
+
+ while (mask) {
+ unsigned i = u_bit_scan(&mask);
+
+ if (images->views[i].resource == buf) {
+ if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
+ si_mark_image_range_valid(&images->views[i]);
+
+ si_desc_reset_buffer_offset(
+ ctx, descs->list + i * 8 + 4,
+ old_va, buf);
+ descs->dirty_mask |= 1u << i;
+ sctx->descriptors_dirty |=
+ 1u << si_image_descriptors_idx(shader);
+
+ radeon_add_to_buffer_list_check_mem(
+ &sctx->b, &sctx->b.gfx, rbuffer,
+ RADEON_USAGE_READWRITE,
+ RADEON_PRIO_SAMPLER_BUFFER, true);
+ }
}
}
}
view->resource->target == PIPE_BUFFER)
continue;
- si_set_shader_image(sctx, shader, i, view);
+ si_set_shader_image(sctx, shader, i, view, true);
}
/* Sampler views. */
si_set_sampler_view(sctx, shader, i,
samplers->views[i], true);
}
+
+ si_update_compressed_tex_shader_mask(sctx, shader);
}
}
static void si_mark_shader_pointers_dirty(struct si_context *sctx,
unsigned shader)
{
- struct si_descriptors *descs =
- &sctx->descriptors[SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS];
-
- for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
- descs->pointer_dirty = true;
+ sctx->shader_pointers_dirty |=
+ u_bit_consecutive(SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS,
+ SI_NUM_SHADER_DESCS);
if (shader == PIPE_SHADER_VERTEX)
- sctx->vertex_buffers.pointer_dirty = true;
+ sctx->vertex_buffer_pointer_dirty = sctx->vertex_buffers.buffer != NULL;
si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
}
static void si_shader_userdata_begin_new_cs(struct si_context *sctx)
{
- int i;
-
- for (i = 0; i < SI_NUM_SHADERS; i++) {
- si_mark_shader_pointers_dirty(sctx, i);
- }
- sctx->descriptors[SI_DESCS_RW_BUFFERS].pointer_dirty = true;
+ sctx->shader_pointers_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
+ sctx->vertex_buffer_pointer_dirty = sctx->vertex_buffers.buffer != NULL;
+ si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
}
/* Set a base register address for user data constants in the given shader.
if (*base != new_base) {
*base = new_base;
- if (new_base)
+ if (new_base) {
si_mark_shader_pointers_dirty(sctx, shader);
+
+ if (shader == PIPE_SHADER_VERTEX)
+ sctx->last_vs_state = ~0;
+ }
}
}
void si_shader_change_notify(struct si_context *sctx)
{
/* VS can be bound as VS, ES, or LS. */
- if (sctx->tes_shader.cso)
- si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
- R_00B530_SPI_SHADER_USER_DATA_LS_0);
- else if (sctx->gs_shader.cso)
+ if (sctx->tes_shader.cso) {
+ if (sctx->b.chip_class >= GFX9) {
+ si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
+ R_00B430_SPI_SHADER_USER_DATA_LS_0);
+ } else {
+ si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
+ R_00B530_SPI_SHADER_USER_DATA_LS_0);
+ }
+ } else if (sctx->gs_shader.cso) {
si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
R_00B330_SPI_SHADER_USER_DATA_ES_0);
- else
+ } else {
si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
R_00B130_SPI_SHADER_USER_DATA_VS_0);
+ }
/* TES can be bound as ES, VS, or not bound. */
if (sctx->tes_shader.cso) {
static void si_emit_shader_pointer(struct si_context *sctx,
struct si_descriptors *desc,
- unsigned sh_base, bool keep_dirty)
+ unsigned sh_base)
{
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
uint64_t va;
- if (!desc->pointer_dirty || !desc->buffer)
- return;
+ assert(desc->buffer);
va = desc->buffer->gpu_address +
desc->buffer_offset;
radeon_emit(cs, (sh_base + desc->shader_userdata_offset - SI_SH_REG_OFFSET) >> 2);
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
-
- desc->pointer_dirty = keep_dirty;
}
void si_emit_graphics_shader_userdata(struct si_context *sctx,
struct r600_atom *atom)
{
- unsigned shader;
+ unsigned mask;
uint32_t *sh_base = sctx->shader_userdata.sh_base;
struct si_descriptors *descs;
descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
- if (descs->pointer_dirty) {
- si_emit_shader_pointer(sctx, descs,
- R_00B030_SPI_SHADER_USER_DATA_PS_0, true);
+ if (sctx->shader_pointers_dirty & (1 << SI_DESCS_RW_BUFFERS)) {
si_emit_shader_pointer(sctx, descs,
- R_00B130_SPI_SHADER_USER_DATA_VS_0, true);
+ R_00B030_SPI_SHADER_USER_DATA_PS_0);
si_emit_shader_pointer(sctx, descs,
- R_00B230_SPI_SHADER_USER_DATA_GS_0, true);
+ R_00B130_SPI_SHADER_USER_DATA_VS_0);
si_emit_shader_pointer(sctx, descs,
- R_00B330_SPI_SHADER_USER_DATA_ES_0, true);
- si_emit_shader_pointer(sctx, descs,
- R_00B430_SPI_SHADER_USER_DATA_HS_0, true);
- descs->pointer_dirty = false;
+ R_00B330_SPI_SHADER_USER_DATA_ES_0);
+
+ /* GFX9 merged LS-HS and ES-GS. Only set RW_BUFFERS for ES and LS. */
+ if (sctx->b.chip_class >= GFX9) {
+ si_emit_shader_pointer(sctx, descs,
+ R_00B430_SPI_SHADER_USER_DATA_LS_0);
+ } else {
+ si_emit_shader_pointer(sctx, descs,
+ R_00B230_SPI_SHADER_USER_DATA_GS_0);
+ si_emit_shader_pointer(sctx, descs,
+ R_00B430_SPI_SHADER_USER_DATA_HS_0);
+ }
}
- descs = &sctx->descriptors[SI_DESCS_FIRST_SHADER];
+ mask = sctx->shader_pointers_dirty &
+ u_bit_consecutive(SI_DESCS_FIRST_SHADER,
+ SI_DESCS_FIRST_COMPUTE - SI_DESCS_FIRST_SHADER);
- for (shader = 0; shader < SI_NUM_GRAPHICS_SHADERS; shader++) {
+ while (mask) {
+ unsigned i = u_bit_scan(&mask);
+ unsigned shader = (i - SI_DESCS_FIRST_SHADER) / SI_NUM_SHADER_DESCS;
unsigned base = sh_base[shader];
- unsigned i;
- if (!base)
- continue;
+ if (base)
+ si_emit_shader_pointer(sctx, descs + i, base);
+ }
+ sctx->shader_pointers_dirty &=
+ ~u_bit_consecutive(SI_DESCS_RW_BUFFERS, SI_DESCS_FIRST_COMPUTE);
- for (i = 0; i < SI_NUM_SHADER_DESCS; i++, descs++)
- si_emit_shader_pointer(sctx, descs, base, false);
+ if (sctx->vertex_buffer_pointer_dirty) {
+ si_emit_shader_pointer(sctx, &sctx->vertex_buffers,
+ sh_base[PIPE_SHADER_VERTEX]);
+ sctx->vertex_buffer_pointer_dirty = false;
}
- si_emit_shader_pointer(sctx, &sctx->vertex_buffers, sh_base[PIPE_SHADER_VERTEX], false);
}
void si_emit_compute_shader_userdata(struct si_context *sctx)
{
unsigned base = R_00B900_COMPUTE_USER_DATA_0;
- struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_FIRST_COMPUTE];
+ struct si_descriptors *descs = sctx->descriptors;
+ unsigned compute_mask =
+ u_bit_consecutive(SI_DESCS_FIRST_COMPUTE, SI_NUM_SHADER_DESCS);
+ unsigned mask = sctx->shader_pointers_dirty & compute_mask;
- for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
- si_emit_shader_pointer(sctx, descs, base, false);
+ while (mask) {
+ unsigned i = u_bit_scan(&mask);
+
+ si_emit_shader_pointer(sctx, descs + i, base);
+ }
+ sctx->shader_pointers_dirty &= ~compute_mask;
}
/* INIT/DEINIT/UPLOAD */
unsigned ce_offset = 0;
for (i = 0; i < SI_NUM_SHADERS; i++) {
+ /* GFX9 has only 4KB of CE, while previous chips had 32KB.
+ * Rarely used descriptors don't use CE RAM.
+ */
+ bool big_ce = sctx->b.chip_class <= VI;
+ bool images_use_ce = big_ce;
+ bool shaderbufs_use_ce = big_ce ||
+ i == PIPE_SHADER_COMPUTE;
+ bool samplers_use_ce = big_ce ||
+ i == PIPE_SHADER_FRAGMENT;
+
si_init_buffer_resources(&sctx->const_buffers[i],
si_const_buffer_descriptors(sctx, i),
SI_NUM_CONST_BUFFERS, SI_SGPR_CONST_BUFFERS,
si_shader_buffer_descriptors(sctx, i),
SI_NUM_SHADER_BUFFERS, SI_SGPR_SHADER_BUFFERS,
RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RW_BUFFER,
- &ce_offset);
+ shaderbufs_use_ce ? &ce_offset : NULL);
si_init_descriptors(si_sampler_descriptors(sctx, i),
SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS,
- null_texture_descriptor, &ce_offset);
+ null_texture_descriptor,
+ samplers_use_ce ? &ce_offset : NULL);
si_init_descriptors(si_image_descriptors(sctx, i),
SI_SGPR_IMAGES, 8, SI_NUM_IMAGES,
- null_image_descriptor, &ce_offset);
+ null_image_descriptor,
+ images_use_ce ? &ce_offset : NULL);
}
si_init_buffer_resources(&sctx->rw_buffers,
&sctx->descriptors[SI_DESCS_RW_BUFFERS],
SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
- RADEON_USAGE_READWRITE, RADEON_PRIO_RINGS_STREAMOUT,
+ RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS,
&ce_offset);
si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
4, SI_NUM_VERTEX_BUFFERS, NULL, NULL);
sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
- assert(ce_offset <= 32768);
+ if (sctx->b.chip_class >= GFX9)
+ assert(ce_offset <= 4096);
+ else
+ assert(ce_offset <= 32768);
/* Set pipe_context functions. */
sctx->b.b.bind_sampler_states = si_bind_sampler_states;
/* Set default and immutable mappings. */
si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
- si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
- si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
+
+ if (sctx->b.chip_class >= GFX9) {
+ si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL,
+ R_00B430_SPI_SHADER_USER_DATA_LS_0);
+ si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY,
+ R_00B330_SPI_SHADER_USER_DATA_ES_0);
+ } else {
+ si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL,
+ R_00B430_SPI_SHADER_USER_DATA_HS_0);
+ si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY,
+ R_00B230_SPI_SHADER_USER_DATA_GS_0);
+ }
si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
}
const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE);
unsigned dirty = sctx->descriptors_dirty & mask;
+ /* Assume nothing will go wrong: */
+ sctx->shader_pointers_dirty |= dirty;
+
while (dirty) {
unsigned i = u_bit_scan(&dirty);
}
sctx->descriptors_dirty &= ~mask;
-
- return si_upload_vertex_buffer_descriptors(sctx);
+ return true;
}
bool si_upload_compute_shader_descriptors(struct si_context *sctx)
SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE);
unsigned dirty = sctx->descriptors_dirty & mask;
+ /* Assume nothing will go wrong: */
+ sctx->shader_pointers_dirty |= dirty;
+
while (dirty) {
unsigned i = u_bit_scan(&dirty);
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