radeonsi/gfx10: mask DCC tile swizzle by alignment

[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 262f7e88c93bba1349e88bb27dfdd9f378f950c2..5a8c4acc53a94c45ee248f944c11cccfe8a5de68 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -351,7 +351,9 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
                                assert(base_level_info->mode == RADEON_SURF_MODE_2D);
                        }
 
-                       meta_va |= (uint32_t)tex->surface.tile_swizzle << 8;
+                       unsigned dcc_tile_swizzle = tex->surface.tile_swizzle << 8;
+                       dcc_tile_swizzle &= tex->surface.dcc_alignment - 1;
+                       meta_va |= dcc_tile_swizzle;
                } else if (vi_tc_compat_htile_enabled(tex, first_level)) {
                        meta_va = tex->buffer.gpu_address + tex->htile_offset;
                }