* Authors:
* Marek Olšák <marek.olsak@amd.com>
*/
-#include "../radeon/r600_cs.h"
-#include "radeonsi_pipe.h"
-#include "radeonsi_resource.h"
-#include "radeonsi_shader.h"
-#include "util/u_memory.h"
-
-#define SI_NUM_CONTEXTS 16
+/* Resource binding slots and sampler states (each described with 8 or
+ * 4 dwords) are stored in lists in memory which is accessed by shaders
+ * using scalar load instructions.
+ *
+ * This file is responsible for managing such lists. It keeps a copy of all
+ * descriptors in CPU memory and re-uploads a whole list if some slots have
+ * been changed.
+ *
+ * This code is also reponsible for updating shader pointers to those lists.
+ *
+ * Note that CP DMA can't be used for updating the lists, because a GPU hang
+ * could leave the list in a mid-IB state and the next IB would get wrong
+ * descriptors and the whole context would be unusable at that point.
+ * (Note: The register shadowing can't be used due to the same reason)
+ *
+ * Also, uploading descriptors to newly allocated memory doesn't require
+ * a KCACHE flush.
+ *
+ *
+ * Possible scenarios for one 16 dword image+sampler slot:
+ *
+ * | Image | w/ FMASK | Buffer | NULL
+ * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
+ * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
+ * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
+ * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
+ *
+ * FMASK implies MSAA, therefore no sampler state.
+ * Sampler states are never unbound except when FMASK is bound.
+ */
-static uint32_t null_desc[8]; /* zeros */
+#include "radeon/r600_cs.h"
+#include "si_pipe.h"
+#include "si_shader.h"
+#include "sid.h"
-/* Set this if you want the 3D engine to wait until CP DMA is done.
- * It should be set on the last CP DMA packet. */
-#define R600_CP_DMA_SYNC (1 << 0) /* R600+ */
+#include "util/u_memory.h"
+#include "util/u_upload_mgr.h"
-/* Set this if the source data was used as a destination in a previous CP DMA
- * packet. It's for preventing a read-after-write (RAW) hazard between two
- * CP DMA packets. */
-#define SI_CP_DMA_RAW_WAIT (1 << 1) /* SI+ */
-/* Emit a CP DMA packet to do a copy from one buffer to another.
- * The size must fit in bits [20:0]. Notes:
+/* NULL image and buffer descriptor for textures (alpha = 1) and images
+ * (alpha = 0).
+ *
+ * For images, all fields must be zero except for the swizzle, which
+ * supports arbitrary combinations of 0s and 1s. The texture type must be
+ * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
+ *
+ * For buffers, all fields must be zero. If they are not, the hw hangs.
+ *
+ * This is the only reason why the buffer descriptor must be in words [4:7].
*/
-static void si_emit_cp_dma_copy_buffer(struct r600_context *rctx,
- uint64_t dst_va, uint64_t src_va,
- unsigned size, unsigned flags)
-{
- struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
- uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? PKT3_CP_DMA_CP_SYNC : 0;
- uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? PKT3_CP_DMA_CMD_RAW_WAIT : 0;
-
- assert(size);
- assert((size & ((1<<21)-1)) == size);
-
- if (rctx->b.chip_class >= CIK) {
- radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
- radeon_emit(cs, sync_flag); /* CP_SYNC [31] */
- radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
- radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
- radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
- radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
- radeon_emit(cs, size | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
- } else {
- radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
- radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
- radeon_emit(cs, sync_flag | ((src_va >> 32) & 0xffff)); /* CP_SYNC [31] | SRC_ADDR_HI [15:0] */
- radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
- radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
- radeon_emit(cs, size | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
- }
-}
-
-/* Emit a CP DMA packet to clear a buffer. The size must fit in bits [20:0]. */
-static void si_emit_cp_dma_clear_buffer(struct r600_context *rctx,
- uint64_t dst_va, unsigned size,
- uint32_t clear_value, unsigned flags)
-{
- struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
- uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? PKT3_CP_DMA_CP_SYNC : 0;
- uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? PKT3_CP_DMA_CMD_RAW_WAIT : 0;
-
- assert(size);
- assert((size & ((1<<21)-1)) == size);
-
- if (rctx->b.chip_class >= CIK) {
- radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
- radeon_emit(cs, sync_flag | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
- radeon_emit(cs, clear_value); /* DATA [31:0] */
- radeon_emit(cs, 0);
- radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
- radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [15:0] */
- radeon_emit(cs, size | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
- } else {
- radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
- radeon_emit(cs, clear_value); /* DATA [31:0] */
- radeon_emit(cs, sync_flag | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
- radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
- radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
- radeon_emit(cs, size | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
- }
-}
-
-static void si_init_descriptors(struct r600_context *rctx,
- struct si_descriptors *desc,
- unsigned shader_userdata_reg,
+static uint32_t null_texture_descriptor[8] = {
+ 0,
+ 0,
+ 0,
+ S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) |
+ S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
+ /* the rest must contain zeros, which is also used by the buffer
+ * descriptor */
+};
+
+static uint32_t null_image_descriptor[8] = {
+ 0,
+ 0,
+ 0,
+ S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
+ /* the rest must contain zeros, which is also used by the buffer
+ * descriptor */
+};
+
+static void si_init_descriptors(struct si_descriptors *desc,
+ unsigned shader_userdata_index,
unsigned element_dw_size,
unsigned num_elements,
- void (*emit_func)(struct r600_context *ctx, struct r600_atom *state))
+ const uint32_t *null_descriptor)
{
- uint64_t va;
+ int i;
assert(num_elements <= sizeof(desc->enabled_mask)*8);
- assert(num_elements <= sizeof(desc->dirty_mask)*8);
- desc->atom.emit = (void*)emit_func;
- desc->shader_userdata_reg = shader_userdata_reg;
+ desc->list = CALLOC(num_elements, element_dw_size * 4);
desc->element_dw_size = element_dw_size;
desc->num_elements = num_elements;
- desc->context_size = num_elements * element_dw_size * 4;
-
- desc->buffer = (struct r600_resource*)
- pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
- PIPE_USAGE_STATIC,
- SI_NUM_CONTEXTS * desc->context_size);
-
- r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, desc->buffer, RADEON_USAGE_READWRITE);
- va = r600_resource_va(rctx->b.b.screen, &desc->buffer->b.b);
-
- /* We don't check for CS space here, because this should be called
- * only once at context initialization. */
- si_emit_cp_dma_clear_buffer(rctx, va, desc->buffer->b.b.width0, 0,
- R600_CP_DMA_SYNC);
+ desc->list_dirty = true; /* upload the list before the next draw */
+ desc->shader_userdata_offset = shader_userdata_index * 4;
+
+ /* Initialize the array to NULL descriptors if the element size is 8. */
+ if (null_descriptor) {
+ assert(element_dw_size % 8 == 0);
+ for (i = 0; i < num_elements * element_dw_size / 8; i++)
+ memcpy(desc->list + i * 8, null_descriptor,
+ 8 * 4);
+ }
}
static void si_release_descriptors(struct si_descriptors *desc)
{
pipe_resource_reference((struct pipe_resource**)&desc->buffer, NULL);
+ FREE(desc->list);
}
-static void si_update_descriptors(struct r600_context *rctx,
+static bool si_upload_descriptors(struct si_context *sctx,
struct si_descriptors *desc)
{
- if (desc->dirty_mask) {
- desc->atom.num_dw =
- 7 + /* copy */
- (4 + desc->element_dw_size) * util_bitcount(desc->dirty_mask) + /* update */
- 4; /* pointer update */
- desc->atom.dirty = true;
- /* The descriptors are read with the K cache. */
- rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
- } else {
- desc->atom.dirty = false;
+ unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
+ void *ptr;
+
+ if (!desc->list_dirty)
+ return true;
+
+ u_upload_alloc(sctx->b.uploader, 0, list_size, 256,
+ &desc->buffer_offset,
+ (struct pipe_resource**)&desc->buffer, &ptr);
+ if (!desc->buffer)
+ return false; /* skip the draw call */
+
+ util_memcpy_cpu_to_le32(ptr, desc->list, list_size);
+
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
+ RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
+
+ desc->list_dirty = false;
+ desc->pointer_dirty = true;
+ si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
+ return true;
+}
+
+/* SAMPLER VIEWS */
+
+static void si_release_sampler_views(struct si_sampler_views *views)
+{
+ int i;
+
+ for (i = 0; i < Elements(views->views); i++) {
+ pipe_sampler_view_reference(&views->views[i], NULL);
}
+ si_release_descriptors(&views->desc);
}
-static void si_emit_shader_pointer(struct r600_context *rctx,
- struct si_descriptors *desc)
+static void si_sampler_view_add_buffer(struct si_context *sctx,
+ struct pipe_resource *resource)
{
- struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
- uint64_t va = r600_resource_va(rctx->b.b.screen, &desc->buffer->b.b) +
- desc->current_context_id * desc->context_size;
+ struct r600_resource *rres = (struct r600_resource*)resource;
- radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
- radeon_emit(cs, (desc->shader_userdata_reg - SI_SH_REG_OFFSET) >> 2);
- radeon_emit(cs, va);
- radeon_emit(cs, va >> 32);
+ if (!resource)
+ return;
+
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, rres,
+ RADEON_USAGE_READ,
+ r600_get_sampler_view_priority(rres));
}
-static void si_emit_descriptors(struct r600_context *rctx,
- struct si_descriptors *desc,
- uint32_t **descriptors)
+static void si_sampler_views_begin_new_cs(struct si_context *sctx,
+ struct si_sampler_views *views)
{
- struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
- uint64_t va_base;
- int packet_start;
- int packet_size = 0;
- int last_index = desc->num_elements; /* point to a non-existing element */
- unsigned dirty_mask = desc->dirty_mask;
- unsigned new_context_id = (desc->current_context_id + 1) % SI_NUM_CONTEXTS;
+ uint64_t mask = views->desc.enabled_mask;
- assert(dirty_mask);
+ /* Add buffers to the CS. */
+ while (mask) {
+ int i = u_bit_scan64(&mask);
- va_base = r600_resource_va(rctx->b.b.screen, &desc->buffer->b.b);
+ si_sampler_view_add_buffer(sctx, views->views[i]->texture);
+ }
- /* Copy the descriptors to a new context slot. */
- /* XXX Consider using TC or L2 for this copy on CIK. */
- si_emit_cp_dma_copy_buffer(rctx,
- va_base + new_context_id * desc->context_size,
- va_base + desc->current_context_id * desc->context_size,
- desc->context_size, R600_CP_DMA_SYNC);
+ if (!views->desc.buffer)
+ return;
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, views->desc.buffer,
+ RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
+}
- va_base += new_context_id * desc->context_size;
+static void si_set_sampler_view(struct si_context *sctx,
+ struct si_sampler_views *views,
+ unsigned slot, struct pipe_sampler_view *view)
+{
+ struct si_sampler_view *rview = (struct si_sampler_view*)view;
+
+ if (view && view->texture && view->texture->target != PIPE_BUFFER &&
+ G_008F28_COMPRESSION_EN(rview->state[6]) &&
+ ((struct r600_texture*)view->texture)->dcc_offset == 0) {
+ rview->state[6] &= C_008F28_COMPRESSION_EN &
+ C_008F28_ALPHA_IS_ON_MSB;
+ } else if (views->views[slot] == view)
+ return;
- /* Update the descriptors.
- * Updates of consecutive descriptors are merged to one WRITE_DATA packet.
- *
- * XXX When unbinding lots of resources, consider clearing the memory
- * with CP DMA instead of emitting zeros.
- */
- while (dirty_mask) {
- int i = u_bit_scan(&dirty_mask);
+ if (view) {
+ struct r600_texture *rtex = (struct r600_texture *)view->texture;
+
+ si_sampler_view_add_buffer(sctx, view->texture);
- assert(i < desc->num_elements);
+ pipe_sampler_view_reference(&views->views[slot], view);
+ memcpy(views->desc.list + slot * 16, rview->state, 8*4);
- if (last_index+1 == i && packet_size) {
- /* Append new data at the end of the last packet. */
- packet_size += desc->element_dw_size;
- cs->buf[packet_start] = PKT3(PKT3_WRITE_DATA, packet_size, 0);
+ if (view->texture && view->texture->target != PIPE_BUFFER &&
+ rtex->fmask.size) {
+ memcpy(views->desc.list + slot*16 + 8,
+ rview->fmask_state, 8*4);
} else {
- /* Start a new packet. */
- uint64_t va = va_base + i * desc->element_dw_size * 4;
-
- packet_start = cs->cdw;
- packet_size = 2 + desc->element_dw_size;
-
- radeon_emit(cs, PKT3(PKT3_WRITE_DATA, packet_size, 0));
- radeon_emit(cs, PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_TC_OR_L2) |
- PKT3_WRITE_DATA_WR_CONFIRM |
- PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME));
- radeon_emit(cs, va & 0xFFFFFFFFUL);
- radeon_emit(cs, (va >> 32UL) & 0xFFFFFFFFUL);
- }
+ /* Disable FMASK and bind sampler state in [12:15]. */
+ memcpy(views->desc.list + slot*16 + 8,
+ null_texture_descriptor, 4*4);
- radeon_emit_array(cs, descriptors[i], desc->element_dw_size);
+ if (views->sampler_states[slot])
+ memcpy(views->desc.list + slot*16 + 12,
+ views->sampler_states[slot], 4*4);
+ }
- last_index = i;
+ views->desc.enabled_mask |= 1llu << slot;
+ } else {
+ pipe_sampler_view_reference(&views->views[slot], NULL);
+ memcpy(views->desc.list + slot*16, null_texture_descriptor, 8*4);
+ /* Only clear the lower dwords of FMASK. */
+ memcpy(views->desc.list + slot*16 + 8, null_texture_descriptor, 4*4);
+ views->desc.enabled_mask &= ~(1llu << slot);
}
- desc->dirty_mask = 0;
- desc->current_context_id = new_context_id;
-
- /* Now update the shader userdata pointer. */
- si_emit_shader_pointer(rctx, desc);
+ views->desc.list_dirty = true;
}
-static unsigned si_get_shader_user_data_base(unsigned shader)
+static bool is_compressed_colortex(struct r600_texture *rtex)
{
- switch (shader) {
- case PIPE_SHADER_VERTEX:
- return R_00B130_SPI_SHADER_USER_DATA_VS_0;
- case PIPE_SHADER_GEOMETRY:
- return R_00B230_SPI_SHADER_USER_DATA_GS_0;
- case PIPE_SHADER_FRAGMENT:
- return R_00B030_SPI_SHADER_USER_DATA_PS_0;
- default:
- assert(0);
- return 0;
- }
+ return rtex->cmask.size || rtex->fmask.size ||
+ (rtex->dcc_offset && rtex->dirty_level_mask);
}
-/* SAMPLER VIEWS */
-
-static void si_emit_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
+static void si_set_sampler_views(struct pipe_context *ctx,
+ unsigned shader, unsigned start,
+ unsigned count,
+ struct pipe_sampler_view **views)
{
- struct si_sampler_views *views = (struct si_sampler_views*)atom;
+ struct si_context *sctx = (struct si_context *)ctx;
+ struct si_textures_info *samplers = &sctx->samplers[shader];
+ int i;
- si_emit_descriptors(rctx, &views->desc, views->desc_data);
+ if (!count || shader >= SI_NUM_SHADERS)
+ return;
+
+ for (i = 0; i < count; i++) {
+ unsigned slot = start + i;
+
+ if (!views || !views[i]) {
+ samplers->depth_texture_mask &= ~(1 << slot);
+ samplers->compressed_colortex_mask &= ~(1 << slot);
+ si_set_sampler_view(sctx, &samplers->views, slot, NULL);
+ continue;
+ }
+
+ si_set_sampler_view(sctx, &samplers->views, slot, views[i]);
+
+ if (views[i]->texture && views[i]->texture->target != PIPE_BUFFER) {
+ struct r600_texture *rtex =
+ (struct r600_texture*)views[i]->texture;
+
+ if (rtex->is_depth && !rtex->is_flushing_texture) {
+ samplers->depth_texture_mask |= 1 << slot;
+ } else {
+ samplers->depth_texture_mask &= ~(1 << slot);
+ }
+ if (is_compressed_colortex(rtex)) {
+ samplers->compressed_colortex_mask |= 1 << slot;
+ } else {
+ samplers->compressed_colortex_mask &= ~(1 << slot);
+ }
+ } else {
+ samplers->depth_texture_mask &= ~(1 << slot);
+ samplers->compressed_colortex_mask &= ~(1 << slot);
+ }
+ }
}
-static void si_init_sampler_views(struct r600_context *rctx,
- struct si_sampler_views *views,
- unsigned shader)
+static void
+si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
{
- si_init_descriptors(rctx, &views->desc,
- si_get_shader_user_data_base(shader) +
- SI_SGPR_RESOURCE * 4,
- 8, NUM_SAMPLER_VIEWS, si_emit_sampler_views);
+ uint64_t mask = samplers->views.desc.enabled_mask;
+
+ while (mask) {
+ int i = u_bit_scan64(&mask);
+ struct pipe_resource *res = samplers->views.views[i]->texture;
+
+ if (res && res->target != PIPE_BUFFER) {
+ struct r600_texture *rtex = (struct r600_texture *)res;
+
+ if (is_compressed_colortex(rtex)) {
+ samplers->compressed_colortex_mask |= 1 << i;
+ } else {
+ samplers->compressed_colortex_mask &= ~(1 << i);
+ }
+ }
+ }
}
-static void si_release_sampler_views(struct si_sampler_views *views)
+/* IMAGE VIEWS */
+
+static void
+si_release_image_views(struct si_images_info *images)
{
- int i;
+ unsigned i;
- for (i = 0; i < Elements(views->views); i++) {
- pipe_sampler_view_reference(&views->views[i], NULL);
+ for (i = 0; i < SI_NUM_IMAGES; ++i) {
+ struct pipe_image_view *view = &images->views[i];
+
+ pipe_resource_reference(&view->resource, NULL);
}
- si_release_descriptors(&views->desc);
+
+ si_release_descriptors(&images->desc);
}
-static void si_sampler_views_begin_new_cs(struct r600_context *rctx,
- struct si_sampler_views *views)
+static void
+si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info *images)
{
- unsigned mask = views->desc.enabled_mask;
+ uint mask = images->desc.enabled_mask;
- /* Add relocations to the CS. */
+ /* Add buffers to the CS. */
while (mask) {
int i = u_bit_scan(&mask);
- struct si_pipe_sampler_view *rview =
- (struct si_pipe_sampler_view*)views->views[i];
+ struct pipe_image_view *view = &images->views[i];
+
+ assert(view->resource);
- r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ);
+ si_sampler_view_add_buffer(sctx, view->resource);
}
- r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, views->desc.buffer, RADEON_USAGE_READWRITE);
+ if (images->desc.buffer) {
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ images->desc.buffer,
+ RADEON_USAGE_READ,
+ RADEON_PRIO_DESCRIPTORS);
+ }
+}
+
+static void
+si_disable_shader_image(struct si_images_info *images, unsigned slot)
+{
+ if (images->desc.enabled_mask & (1llu << slot)) {
+ pipe_resource_reference(&images->views[slot].resource, NULL);
+ images->compressed_colortex_mask &= ~(1 << slot);
- si_emit_shader_pointer(rctx, &views->desc);
+ memcpy(images->desc.list + slot*8, null_image_descriptor, 8*4);
+ images->desc.enabled_mask &= ~(1llu << slot);
+ images->desc.list_dirty = true;
+ }
}
-void si_set_sampler_view(struct r600_context *rctx, unsigned shader,
- unsigned slot, struct pipe_sampler_view *view,
- unsigned *view_desc)
+static void
+si_set_shader_images(struct pipe_context *pipe, unsigned shader,
+ unsigned start_slot, unsigned count,
+ struct pipe_image_view *views)
{
- struct si_sampler_views *views = &rctx->samplers[shader].views;
+ struct si_context *ctx = (struct si_context *)pipe;
+ struct si_screen *screen = ctx->screen;
+ struct si_images_info *images = &ctx->images[shader];
+ unsigned i, slot;
+
+ assert(shader < SI_NUM_SHADERS);
- if (views->views[slot] == view)
+ if (!count)
return;
- if (view) {
- struct si_pipe_sampler_view *rview =
- (struct si_pipe_sampler_view*)view;
+ assert(start_slot + count <= SI_NUM_IMAGES);
- r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ);
+ for (i = 0, slot = start_slot; i < count; ++i, ++slot) {
+ struct r600_resource *res;
- pipe_sampler_view_reference(&views->views[slot], view);
- views->desc_data[slot] = view_desc;
- views->desc.enabled_mask |= 1 << slot;
- } else {
- pipe_sampler_view_reference(&views->views[slot], NULL);
- views->desc_data[slot] = null_desc;
- views->desc.enabled_mask &= ~(1 << slot);
+ if (!views || !views[i].resource) {
+ si_disable_shader_image(images, slot);
+ continue;
+ }
+
+ res = (struct r600_resource *)views[i].resource;
+ util_copy_image_view(&images->views[slot], &views[i]);
+
+ si_sampler_view_add_buffer(ctx, &res->b.b);
+
+ if (res->b.b.target == PIPE_BUFFER) {
+ si_make_buffer_descriptor(screen, res,
+ views[i].format,
+ views[i].u.buf.first_element,
+ views[i].u.buf.last_element,
+ images->desc.list + slot * 8);
+ images->compressed_colortex_mask &= ~(1 << slot);
+ } else {
+ static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
+ struct r600_texture *tex = (struct r600_texture *)res;
+ unsigned level;
+ unsigned width, height, depth;
+
+ assert(!tex->is_depth);
+ assert(tex->fmask.size == 0);
+
+ if (tex->dcc_offset &&
+ views[i].access & PIPE_IMAGE_ACCESS_WRITE)
+ r600_texture_disable_dcc(&screen->b, tex);
+
+ if (is_compressed_colortex(tex)) {
+ images->compressed_colortex_mask |= 1 << slot;
+ } else {
+ images->compressed_colortex_mask &= ~(1 << slot);
+ }
+
+ /* Always force the base level to the selected level.
+ *
+ * This is required for 3D textures, where otherwise
+ * selecting a single slice for non-layered bindings
+ * fails. It doesn't hurt the other targets.
+ */
+ level = views[i].u.tex.level;
+ width = u_minify(res->b.b.width0, level);
+ height = u_minify(res->b.b.height0, level);
+ depth = u_minify(res->b.b.depth0, level);
+
+ si_make_texture_descriptor(screen, tex, false, res->b.b.target,
+ views[i].format, swizzle,
+ level, 0, 0,
+ views[i].u.tex.first_layer, views[i].u.tex.last_layer,
+ width, height, depth,
+ images->desc.list + slot * 8,
+ NULL);
+ }
+
+ images->desc.enabled_mask |= 1llu << slot;
+ images->desc.list_dirty = true;
}
+}
+
+static void
+si_images_update_compressed_colortex_mask(struct si_images_info *images)
+{
+ uint64_t mask = images->desc.enabled_mask;
+
+ while (mask) {
+ int i = u_bit_scan64(&mask);
+ struct pipe_resource *res = images->views[i].resource;
+
+ if (res && res->target != PIPE_BUFFER) {
+ struct r600_texture *rtex = (struct r600_texture *)res;
- views->desc.dirty_mask |= 1 << slot;
- si_update_descriptors(rctx, &views->desc);
+ if (is_compressed_colortex(rtex)) {
+ images->compressed_colortex_mask |= 1 << i;
+ } else {
+ images->compressed_colortex_mask &= ~(1 << i);
+ }
+ }
+ }
}
-/* BUFFER RESOURCES */
+/* SAMPLER STATES */
-static void si_emit_buffer_resources(struct r600_context *rctx, struct r600_atom *atom)
+static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
+ unsigned start, unsigned count, void **states)
{
- struct si_buffer_resources *buffers = (struct si_buffer_resources*)atom;
+ struct si_context *sctx = (struct si_context *)ctx;
+ struct si_textures_info *samplers = &sctx->samplers[shader];
+ struct si_descriptors *desc = &samplers->views.desc;
+ struct si_sampler_state **sstates = (struct si_sampler_state**)states;
+ int i;
+
+ if (!count || shader >= SI_NUM_SHADERS)
+ return;
+
+ for (i = 0; i < count; i++) {
+ unsigned slot = start + i;
+
+ if (!sstates[i] ||
+ sstates[i] == samplers->views.sampler_states[slot])
+ continue;
+
+ samplers->views.sampler_states[slot] = sstates[i];
+
+ /* If FMASK is bound, don't overwrite it.
+ * The sampler state will be set after FMASK is unbound.
+ */
+ if (samplers->views.views[i] &&
+ samplers->views.views[i]->texture &&
+ samplers->views.views[i]->texture->target != PIPE_BUFFER &&
+ ((struct r600_texture*)samplers->views.views[i]->texture)->fmask.size)
+ continue;
- si_emit_descriptors(rctx, &buffers->desc, buffers->desc_data);
+ memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
+ desc->list_dirty = true;
+ }
}
-static void si_init_buffer_resources(struct r600_context *rctx,
- struct si_buffer_resources *buffers,
- unsigned num_buffers, unsigned shader,
+/* BUFFER RESOURCES */
+
+static void si_init_buffer_resources(struct si_buffer_resources *buffers,
+ unsigned num_buffers,
unsigned shader_userdata_index,
- enum radeon_bo_usage shader_usage)
+ enum radeon_bo_usage shader_usage,
+ enum radeon_bo_priority priority)
{
- int i;
-
- buffers->num_buffers = num_buffers;
buffers->shader_usage = shader_usage;
+ buffers->priority = priority;
buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
- buffers->desc_storage = CALLOC(num_buffers, sizeof(uint32_t) * 4);
- /* si_emit_descriptors only accepts an array of arrays.
- * This adds such an array. */
- buffers->desc_data = CALLOC(num_buffers, sizeof(uint32_t*));
- for (i = 0; i < num_buffers; i++) {
- buffers->desc_data[i] = &buffers->desc_storage[i*4];
- }
-
- si_init_descriptors(rctx, &buffers->desc,
- si_get_shader_user_data_base(shader) +
- shader_userdata_index*4, 4, num_buffers,
- si_emit_buffer_resources);
+ si_init_descriptors(&buffers->desc, shader_userdata_index, 4,
+ num_buffers, NULL);
}
static void si_release_buffer_resources(struct si_buffer_resources *buffers)
{
int i;
- for (i = 0; i < Elements(buffers->buffers); i++) {
+ for (i = 0; i < buffers->desc.num_elements; i++) {
pipe_resource_reference(&buffers->buffers[i], NULL);
}
FREE(buffers->buffers);
- FREE(buffers->desc_storage);
- FREE(buffers->desc_data);
si_release_descriptors(&buffers->desc);
}
-static void si_buffer_resources_begin_new_cs(struct r600_context *rctx,
+static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
struct si_buffer_resources *buffers)
{
- unsigned mask = buffers->desc.enabled_mask;
+ uint64_t mask = buffers->desc.enabled_mask;
- /* Add relocations to the CS. */
+ /* Add buffers to the CS. */
while (mask) {
- int i = u_bit_scan(&mask);
+ int i = u_bit_scan64(&mask);
- r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
(struct r600_resource*)buffers->buffers[i],
- buffers->shader_usage);
+ buffers->shader_usage, buffers->priority);
+ }
+
+ if (!buffers->desc.buffer)
+ return;
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ buffers->desc.buffer, RADEON_USAGE_READWRITE,
+ RADEON_PRIO_DESCRIPTORS);
+}
+
+/* VERTEX BUFFERS */
+
+static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
+{
+ struct si_descriptors *desc = &sctx->vertex_buffers;
+ int count = sctx->vertex_elements ? sctx->vertex_elements->count : 0;
+ int i;
+
+ for (i = 0; i < count; i++) {
+ int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
+
+ if (vb >= Elements(sctx->vertex_buffer))
+ continue;
+ if (!sctx->vertex_buffer[vb].buffer)
+ continue;
+
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ (struct r600_resource*)sctx->vertex_buffer[vb].buffer,
+ RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
}
- r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
- buffers->desc.buffer, RADEON_USAGE_READWRITE);
+ if (!desc->buffer)
+ return;
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ desc->buffer, RADEON_USAGE_READ,
+ RADEON_PRIO_DESCRIPTORS);
+}
+
+static bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
+{
+ struct si_descriptors *desc = &sctx->vertex_buffers;
+ bool bound[SI_NUM_VERTEX_BUFFERS] = {};
+ unsigned i, count = sctx->vertex_elements->count;
+ uint64_t va;
+ uint32_t *ptr;
+
+ if (!sctx->vertex_buffers_dirty)
+ return true;
+ if (!count || !sctx->vertex_elements)
+ return true;
+
+ /* Vertex buffer descriptors are the only ones which are uploaded
+ * directly through a staging buffer and don't go through
+ * the fine-grained upload path.
+ */
+ u_upload_alloc(sctx->b.uploader, 0, count * 16, 256, &desc->buffer_offset,
+ (struct pipe_resource**)&desc->buffer, (void**)&ptr);
+ if (!desc->buffer)
+ return false;
+
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ desc->buffer, RADEON_USAGE_READ,
+ RADEON_PRIO_DESCRIPTORS);
+
+ assert(count <= SI_NUM_VERTEX_BUFFERS);
+
+ for (i = 0; i < count; i++) {
+ struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i];
+ struct pipe_vertex_buffer *vb;
+ struct r600_resource *rbuffer;
+ unsigned offset;
+ uint32_t *desc = &ptr[i*4];
+
+ if (ve->vertex_buffer_index >= Elements(sctx->vertex_buffer)) {
+ memset(desc, 0, 16);
+ continue;
+ }
+
+ vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
+ rbuffer = (struct r600_resource*)vb->buffer;
+ if (!rbuffer) {
+ memset(desc, 0, 16);
+ continue;
+ }
+
+ offset = vb->buffer_offset + ve->src_offset;
+ va = rbuffer->gpu_address + offset;
+
+ /* Fill in T# buffer resource description */
+ desc[0] = va;
+ desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
+ S_008F04_STRIDE(vb->stride);
+
+ if (sctx->b.chip_class <= CIK && vb->stride)
+ /* Round up by rounding down and adding 1 */
+ desc[2] = (vb->buffer->width0 - offset -
+ sctx->vertex_elements->format_size[i]) /
+ vb->stride + 1;
+ else
+ desc[2] = vb->buffer->width0 - offset;
+
+ desc[3] = sctx->vertex_elements->rsrc_word3[i];
+
+ if (!bound[ve->vertex_buffer_index]) {
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ (struct r600_resource*)vb->buffer,
+ RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
+ bound[ve->vertex_buffer_index] = true;
+ }
+ }
- si_emit_shader_pointer(rctx, &buffers->desc);
+ /* Don't flush the const cache. It would have a very negative effect
+ * on performance (confirmed by testing). New descriptors are always
+ * uploaded to a fresh new buffer, so I don't think flushing the const
+ * cache is needed. */
+ desc->pointer_dirty = true;
+ si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
+ sctx->vertex_buffers_dirty = false;
+ return true;
}
+
/* CONSTANT BUFFERS */
+void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
+ const uint8_t *ptr, unsigned size, uint32_t *const_offset)
+{
+ void *tmp;
+
+ u_upload_alloc(sctx->b.uploader, 0, size, 256, const_offset,
+ (struct pipe_resource**)rbuffer, &tmp);
+ if (rbuffer)
+ util_memcpy_cpu_to_le32(tmp, ptr, size);
+}
+
static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint slot,
struct pipe_constant_buffer *input)
{
- struct r600_context *rctx = (struct r600_context *)ctx;
- struct si_buffer_resources *buffers = &rctx->const_buffers[shader];
+ struct si_context *sctx = (struct si_context *)ctx;
+ struct si_buffer_resources *buffers = &sctx->const_buffers[shader];
if (shader >= SI_NUM_SHADERS)
return;
- assert(slot < buffers->num_buffers);
+ assert(slot < buffers->desc.num_elements);
pipe_resource_reference(&buffers->buffers[slot], NULL);
+ /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
+ * with a NULL buffer). We need to use a dummy buffer instead. */
+ if (sctx->b.chip_class == CIK &&
+ (!input || (!input->buffer && !input->user_buffer)))
+ input = &sctx->null_const_buf;
+
if (input && (input->buffer || input->user_buffer)) {
struct pipe_resource *buffer = NULL;
uint64_t va;
if (input->user_buffer) {
unsigned buffer_offset;
- r600_upload_const_buffer(rctx,
- (struct r600_resource**)&buffer, input->user_buffer,
- input->buffer_size, &buffer_offset);
- va = r600_resource_va(ctx->screen, buffer) + buffer_offset;
+ si_upload_const_buffer(sctx,
+ (struct r600_resource**)&buffer, input->user_buffer,
+ input->buffer_size, &buffer_offset);
+ if (!buffer) {
+ /* Just unbind on failure. */
+ si_set_constant_buffer(ctx, shader, slot, NULL);
+ return;
+ }
+ va = r600_resource(buffer)->gpu_address + buffer_offset;
} else {
pipe_resource_reference(&buffer, input->buffer);
- va = r600_resource_va(ctx->screen, buffer) + input->buffer_offset;
+ va = r600_resource(buffer)->gpu_address + input->buffer_offset;
}
/* Set the descriptor. */
- uint32_t *desc = buffers->desc_data[slot];
+ uint32_t *desc = buffers->desc.list + slot*4;
desc[0] = va;
desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
S_008F04_STRIDE(0);
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
buffers->buffers[slot] = buffer;
- r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
- (struct r600_resource*)buffer, buffers->shader_usage);
- buffers->desc.enabled_mask |= 1 << slot;
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ (struct r600_resource*)buffer,
+ buffers->shader_usage, buffers->priority);
+ buffers->desc.enabled_mask |= 1llu << slot;
} else {
/* Clear the descriptor. */
- memset(buffers->desc_data[slot], 0, sizeof(uint32_t) * 4);
- buffers->desc.enabled_mask &= ~(1 << slot);
+ memset(buffers->desc.list + slot*4, 0, sizeof(uint32_t) * 4);
+ buffers->desc.enabled_mask &= ~(1llu << slot);
}
- buffers->desc.dirty_mask |= 1 << slot;
- si_update_descriptors(rctx, &buffers->desc);
+ buffers->desc.list_dirty = true;
}
-/* INIT/DEINIT */
+/* RING BUFFERS */
-void si_init_all_descriptors(struct r600_context *rctx)
+void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
+ struct pipe_resource *buffer,
+ unsigned stride, unsigned num_records,
+ bool add_tid, bool swizzle,
+ unsigned element_size, unsigned index_stride, uint64_t offset)
+{
+ struct si_context *sctx = (struct si_context *)ctx;
+ struct si_buffer_resources *buffers = &sctx->rw_buffers[shader];
+
+ if (shader >= SI_NUM_SHADERS)
+ return;
+
+ /* The stride field in the resource descriptor has 14 bits */
+ assert(stride < (1 << 14));
+
+ assert(slot < buffers->desc.num_elements);
+ pipe_resource_reference(&buffers->buffers[slot], NULL);
+
+ if (buffer) {
+ uint64_t va;
+
+ va = r600_resource(buffer)->gpu_address + offset;
+
+ switch (element_size) {
+ default:
+ assert(!"Unsupported ring buffer element size");
+ case 0:
+ case 2:
+ element_size = 0;
+ break;
+ case 4:
+ element_size = 1;
+ break;
+ case 8:
+ element_size = 2;
+ break;
+ case 16:
+ element_size = 3;
+ break;
+ }
+
+ switch (index_stride) {
+ default:
+ assert(!"Unsupported ring buffer index stride");
+ case 0:
+ case 8:
+ index_stride = 0;
+ break;
+ case 16:
+ index_stride = 1;
+ break;
+ case 32:
+ index_stride = 2;
+ break;
+ case 64:
+ index_stride = 3;
+ break;
+ }
+
+ if (sctx->b.chip_class >= VI && stride)
+ num_records *= stride;
+
+ /* Set the descriptor. */
+ uint32_t *desc = buffers->desc.list + slot*4;
+ desc[0] = va;
+ desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
+ S_008F04_STRIDE(stride) |
+ S_008F04_SWIZZLE_ENABLE(swizzle);
+ desc[2] = num_records;
+ desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
+ S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
+ S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
+ S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
+ S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+ S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
+ S_008F0C_ELEMENT_SIZE(element_size) |
+ S_008F0C_INDEX_STRIDE(index_stride) |
+ S_008F0C_ADD_TID_ENABLE(add_tid);
+
+ pipe_resource_reference(&buffers->buffers[slot], buffer);
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ (struct r600_resource*)buffer,
+ buffers->shader_usage, buffers->priority);
+ buffers->desc.enabled_mask |= 1llu << slot;
+ } else {
+ /* Clear the descriptor. */
+ memset(buffers->desc.list + slot*4, 0, sizeof(uint32_t) * 4);
+ buffers->desc.enabled_mask &= ~(1llu << slot);
+ }
+
+ buffers->desc.list_dirty = true;
+}
+
+/* STREAMOUT BUFFERS */
+
+static void si_set_streamout_targets(struct pipe_context *ctx,
+ unsigned num_targets,
+ struct pipe_stream_output_target **targets,
+ const unsigned *offsets)
+{
+ struct si_context *sctx = (struct si_context *)ctx;
+ struct si_buffer_resources *buffers = &sctx->rw_buffers[PIPE_SHADER_VERTEX];
+ unsigned old_num_targets = sctx->b.streamout.num_targets;
+ unsigned i, bufidx;
+
+ /* We are going to unbind the buffers. Mark which caches need to be flushed. */
+ if (sctx->b.streamout.num_targets && sctx->b.streamout.begin_emitted) {
+ /* Since streamout uses vector writes which go through TC L2
+ * and most other clients can use TC L2 as well, we don't need
+ * to flush it.
+ *
+ * The only case which requires flushing it is VGT DMA index
+ * fetching, which is a rare case. Thus, flag the TC L2
+ * dirtiness in the resource and handle it when index fetching
+ * is used.
+ */
+ for (i = 0; i < sctx->b.streamout.num_targets; i++)
+ if (sctx->b.streamout.targets[i])
+ r600_resource(sctx->b.streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
+
+ /* Invalidate the scalar cache in case a streamout buffer is
+ * going to be used as a constant buffer.
+ *
+ * Invalidate TC L1, because streamout bypasses it (done by
+ * setting GLC=1 in the store instruction), but it can contain
+ * outdated data of streamout buffers.
+ *
+ * VS_PARTIAL_FLUSH is required if the buffers are going to be
+ * used as an input immediately.
+ */
+ sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
+ SI_CONTEXT_INV_VMEM_L1 |
+ SI_CONTEXT_VS_PARTIAL_FLUSH;
+ }
+
+ /* Streamout buffers must be bound in 2 places:
+ * 1) in VGT by setting the VGT_STRMOUT registers
+ * 2) as shader resources
+ */
+
+ /* Set the VGT regs. */
+ r600_set_streamout_targets(ctx, num_targets, targets, offsets);
+
+ /* Set the shader resources.*/
+ for (i = 0; i < num_targets; i++) {
+ bufidx = SI_SO_BUF_OFFSET + i;
+
+ if (targets[i]) {
+ struct pipe_resource *buffer = targets[i]->buffer;
+ uint64_t va = r600_resource(buffer)->gpu_address;
+
+ /* Set the descriptor.
+ *
+ * On VI, the format must be non-INVALID, otherwise
+ * the buffer will be considered not bound and store
+ * instructions will be no-ops.
+ */
+ uint32_t *desc = buffers->desc.list + bufidx*4;
+ desc[0] = va;
+ desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
+ desc[2] = 0xffffffff;
+ desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
+ S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
+ S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
+ S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
+ S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+
+ /* Set the resource. */
+ pipe_resource_reference(&buffers->buffers[bufidx],
+ buffer);
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ (struct r600_resource*)buffer,
+ buffers->shader_usage, buffers->priority);
+ buffers->desc.enabled_mask |= 1llu << bufidx;
+ } else {
+ /* Clear the descriptor and unset the resource. */
+ memset(buffers->desc.list + bufidx*4, 0,
+ sizeof(uint32_t) * 4);
+ pipe_resource_reference(&buffers->buffers[bufidx],
+ NULL);
+ buffers->desc.enabled_mask &= ~(1llu << bufidx);
+ }
+ }
+ for (; i < old_num_targets; i++) {
+ bufidx = SI_SO_BUF_OFFSET + i;
+ /* Clear the descriptor and unset the resource. */
+ memset(buffers->desc.list + bufidx*4, 0, sizeof(uint32_t) * 4);
+ pipe_resource_reference(&buffers->buffers[bufidx], NULL);
+ buffers->desc.enabled_mask &= ~(1llu << bufidx);
+ }
+
+ buffers->desc.list_dirty = true;
+}
+
+static void si_desc_reset_buffer_offset(struct pipe_context *ctx,
+ uint32_t *desc, uint64_t old_buf_va,
+ struct pipe_resource *new_buf)
+{
+ /* Retrieve the buffer offset from the descriptor. */
+ uint64_t old_desc_va =
+ desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
+
+ assert(old_buf_va <= old_desc_va);
+ uint64_t offset_within_buffer = old_desc_va - old_buf_va;
+
+ /* Update the descriptor. */
+ uint64_t va = r600_resource(new_buf)->gpu_address + offset_within_buffer;
+
+ desc[0] = va;
+ desc[1] = (desc[1] & C_008F04_BASE_ADDRESS_HI) |
+ S_008F04_BASE_ADDRESS_HI(va >> 32);
+}
+
+/* TEXTURE METADATA ENABLE/DISABLE */
+
+/* CMASK can be enabled (for fast clear) and disabled (for texture export)
+ * while the texture is bound, possibly by a different context. In that case,
+ * call this function to update compressed_colortex_masks.
+ */
+void si_update_compressed_colortex_masks(struct si_context *sctx)
+{
+ for (int i = 0; i < SI_NUM_SHADERS; ++i) {
+ si_samplers_update_compressed_colortex_mask(&sctx->samplers[i]);
+ si_images_update_compressed_colortex_mask(&sctx->images[i]);
+ }
+}
+
+/* BUFFER DISCARD/INVALIDATION */
+
+/* Reallocate a buffer a update all resource bindings where the buffer is
+ * bound.
+ *
+ * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
+ * idle by discarding its contents. Apps usually tell us when to do this using
+ * map_buffer flags, for example.
+ */
+static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
+{
+ struct si_context *sctx = (struct si_context*)ctx;
+ struct r600_resource *rbuffer = r600_resource(buf);
+ unsigned i, shader, alignment = rbuffer->buf->alignment;
+ uint64_t old_va = rbuffer->gpu_address;
+ unsigned num_elems = sctx->vertex_elements ?
+ sctx->vertex_elements->count : 0;
+ struct si_sampler_view *view;
+
+ /* Reallocate the buffer in the same pipe_resource. */
+ r600_init_resource(&sctx->screen->b, rbuffer, rbuffer->b.b.width0,
+ alignment, TRUE);
+
+ /* We changed the buffer, now we need to bind it where the old one
+ * was bound. This consists of 2 things:
+ * 1) Updating the resource descriptor and dirtying it.
+ * 2) Adding a relocation to the CS, so that it's usable.
+ */
+
+ /* Vertex buffers. */
+ for (i = 0; i < num_elems; i++) {
+ int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
+
+ if (vb >= Elements(sctx->vertex_buffer))
+ continue;
+ if (!sctx->vertex_buffer[vb].buffer)
+ continue;
+
+ if (sctx->vertex_buffer[vb].buffer == buf) {
+ sctx->vertex_buffers_dirty = true;
+ break;
+ }
+ }
+
+ /* Read/Write buffers. */
+ for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
+ struct si_buffer_resources *buffers = &sctx->rw_buffers[shader];
+ uint64_t mask = buffers->desc.enabled_mask;
+
+ while (mask) {
+ i = u_bit_scan64(&mask);
+ if (buffers->buffers[i] == buf) {
+ si_desc_reset_buffer_offset(ctx, buffers->desc.list + i*4,
+ old_va, buf);
+ buffers->desc.list_dirty = true;
+
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ rbuffer, buffers->shader_usage,
+ buffers->priority);
+
+ if (i >= SI_SO_BUF_OFFSET && shader == PIPE_SHADER_VERTEX) {
+ /* Update the streamout state. */
+ if (sctx->b.streamout.begin_emitted) {
+ r600_emit_streamout_end(&sctx->b);
+ }
+ sctx->b.streamout.append_bitmask =
+ sctx->b.streamout.enabled_mask;
+ r600_streamout_buffers_dirty(&sctx->b);
+ }
+ }
+ }
+ }
+
+ /* Constant buffers. */
+ for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
+ struct si_buffer_resources *buffers = &sctx->const_buffers[shader];
+ uint64_t mask = buffers->desc.enabled_mask;
+
+ while (mask) {
+ unsigned i = u_bit_scan64(&mask);
+ if (buffers->buffers[i] == buf) {
+ si_desc_reset_buffer_offset(ctx, buffers->desc.list + i*4,
+ old_va, buf);
+ buffers->desc.list_dirty = true;
+
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ rbuffer, buffers->shader_usage,
+ buffers->priority);
+ }
+ }
+ }
+
+ /* Texture buffers - update virtual addresses in sampler view descriptors. */
+ LIST_FOR_EACH_ENTRY(view, &sctx->b.texture_buffers, list) {
+ if (view->base.texture == buf) {
+ si_desc_reset_buffer_offset(ctx, &view->state[4], old_va, buf);
+ }
+ }
+ /* Texture buffers - update bindings. */
+ for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
+ struct si_sampler_views *views = &sctx->samplers[shader].views;
+ uint64_t mask = views->desc.enabled_mask;
+
+ while (mask) {
+ unsigned i = u_bit_scan64(&mask);
+ if (views->views[i]->texture == buf) {
+ si_desc_reset_buffer_offset(ctx,
+ views->desc.list +
+ i * 16 + 4,
+ old_va, buf);
+ views->desc.list_dirty = true;
+
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ rbuffer, RADEON_USAGE_READ,
+ RADEON_PRIO_SAMPLER_BUFFER);
+ }
+ }
+ }
+
+ /* Shader images */
+ for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
+ struct si_images_info *images = &sctx->images[shader];
+ unsigned mask = images->desc.enabled_mask;
+
+ while (mask) {
+ unsigned i = u_bit_scan(&mask);
+
+ if (images->views[i].resource == buf) {
+ si_desc_reset_buffer_offset(
+ ctx, images->desc.list + i * 8 + 4,
+ old_va, buf);
+ images->desc.list_dirty = true;
+
+ radeon_add_to_buffer_list(
+ &sctx->b, &sctx->b.gfx, rbuffer,
+ RADEON_USAGE_READWRITE,
+ RADEON_PRIO_SAMPLER_BUFFER);
+ }
+ }
+ }
+}
+
+/* SHADER USER DATA */
+
+static void si_mark_shader_pointers_dirty(struct si_context *sctx,
+ unsigned shader)
+{
+ sctx->const_buffers[shader].desc.pointer_dirty = true;
+ sctx->rw_buffers[shader].desc.pointer_dirty = true;
+ sctx->samplers[shader].views.desc.pointer_dirty = true;
+
+ if (shader == PIPE_SHADER_VERTEX)
+ sctx->vertex_buffers.pointer_dirty = true;
+
+ si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
+}
+
+static void si_shader_userdata_begin_new_cs(struct si_context *sctx)
{
int i;
for (i = 0; i < SI_NUM_SHADERS; i++) {
- si_init_buffer_resources(rctx, &rctx->const_buffers[i],
- NUM_CONST_BUFFERS, i, SI_SGPR_CONST,
- RADEON_USAGE_READ);
+ si_mark_shader_pointers_dirty(sctx, i);
+ }
+}
+
+/* Set a base register address for user data constants in the given shader.
+ * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
+ */
+static void si_set_user_data_base(struct si_context *sctx,
+ unsigned shader, uint32_t new_base)
+{
+ uint32_t *base = &sctx->shader_userdata.sh_base[shader];
+
+ if (*base != new_base) {
+ *base = new_base;
+
+ if (new_base)
+ si_mark_shader_pointers_dirty(sctx, shader);
+ }
+}
+
+/* This must be called when these shaders are changed from non-NULL to NULL
+ * and vice versa:
+ * - geometry shader
+ * - tessellation control shader
+ * - tessellation evaluation shader
+ */
+void si_shader_change_notify(struct si_context *sctx)
+{
+ /* VS can be bound as VS, ES, or LS. */
+ if (sctx->tes_shader.cso)
+ si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
+ R_00B530_SPI_SHADER_USER_DATA_LS_0);
+ else if (sctx->gs_shader.cso)
+ si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
+ R_00B330_SPI_SHADER_USER_DATA_ES_0);
+ else
+ si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
+ R_00B130_SPI_SHADER_USER_DATA_VS_0);
+
+ /* TES can be bound as ES, VS, or not bound. */
+ if (sctx->tes_shader.cso) {
+ if (sctx->gs_shader.cso)
+ si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
+ R_00B330_SPI_SHADER_USER_DATA_ES_0);
+ else
+ si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
+ R_00B130_SPI_SHADER_USER_DATA_VS_0);
+ } else {
+ si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
+ }
+}
+
+static void si_emit_shader_pointer(struct si_context *sctx,
+ struct si_descriptors *desc,
+ unsigned sh_base, bool keep_dirty)
+{
+ struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+ uint64_t va;
+
+ if (!desc->pointer_dirty || !desc->buffer)
+ return;
+
+ va = desc->buffer->gpu_address +
+ desc->buffer_offset;
+
+ radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
+ radeon_emit(cs, (sh_base + desc->shader_userdata_offset - SI_SH_REG_OFFSET) >> 2);
+ radeon_emit(cs, va);
+ radeon_emit(cs, va >> 32);
+
+ desc->pointer_dirty = keep_dirty;
+}
+
+void si_emit_shader_userdata(struct si_context *sctx, struct r600_atom *atom)
+{
+ unsigned i;
+ uint32_t *sh_base = sctx->shader_userdata.sh_base;
+
+ if (sctx->gs_shader.cso) {
+ /* The VS copy shader needs these for clipping, streamout, and rings. */
+ unsigned vs_base = R_00B130_SPI_SHADER_USER_DATA_VS_0;
+ unsigned i = PIPE_SHADER_VERTEX;
+
+ si_emit_shader_pointer(sctx, &sctx->const_buffers[i].desc, vs_base, true);
+ si_emit_shader_pointer(sctx, &sctx->rw_buffers[i].desc, vs_base, true);
+
+ if (sctx->tes_shader.cso) {
+ /* The TESSEVAL shader needs this for the ESGS ring buffer. */
+ si_emit_shader_pointer(sctx, &sctx->rw_buffers[i].desc,
+ R_00B330_SPI_SHADER_USER_DATA_ES_0, true);
+ }
+ } else if (sctx->tes_shader.cso) {
+ /* The TESSEVAL shader needs this for streamout. */
+ si_emit_shader_pointer(sctx, &sctx->rw_buffers[PIPE_SHADER_VERTEX].desc,
+ R_00B130_SPI_SHADER_USER_DATA_VS_0, true);
+ }
+
+ for (i = 0; i < SI_NUM_SHADERS; i++) {
+ unsigned base = sh_base[i];
+
+ if (!base)
+ continue;
- si_init_sampler_views(rctx, &rctx->samplers[i].views, i);
+ if (i != PIPE_SHADER_TESS_EVAL)
+ si_emit_shader_pointer(sctx, &sctx->rw_buffers[i].desc, base, false);
- rctx->atoms.const_buffers[i] = &rctx->const_buffers[i].desc.atom;
- rctx->atoms.sampler_views[i] = &rctx->samplers[i].views.desc.atom;
+ si_emit_shader_pointer(sctx, &sctx->const_buffers[i].desc, base, false);
+ si_emit_shader_pointer(sctx, &sctx->samplers[i].views.desc, base, false);
+ si_emit_shader_pointer(sctx, &sctx->images[i].desc, base, false);
}
+ si_emit_shader_pointer(sctx, &sctx->vertex_buffers, sh_base[PIPE_SHADER_VERTEX], false);
+}
+
+/* INIT/DEINIT/UPLOAD */
+
+void si_init_all_descriptors(struct si_context *sctx)
+{
+ int i;
+
+ for (i = 0; i < SI_NUM_SHADERS; i++) {
+ si_init_buffer_resources(&sctx->const_buffers[i],
+ SI_NUM_CONST_BUFFERS, SI_SGPR_CONST_BUFFERS,
+ RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
+ si_init_buffer_resources(&sctx->rw_buffers[i],
+ SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
+ RADEON_USAGE_READWRITE, RADEON_PRIO_RINGS_STREAMOUT);
+
+ si_init_descriptors(&sctx->samplers[i].views.desc,
+ SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS,
+ null_texture_descriptor);
+
+ si_init_descriptors(&sctx->images[i].desc,
+ SI_SGPR_IMAGES, 8, SI_NUM_IMAGES,
+ null_image_descriptor);
+ }
+
+ si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
+ 4, SI_NUM_VERTEX_BUFFERS, NULL);
/* Set pipe_context functions. */
- rctx->b.b.set_constant_buffer = si_set_constant_buffer;
+ sctx->b.b.bind_sampler_states = si_bind_sampler_states;
+ sctx->b.b.set_shader_images = si_set_shader_images;
+ sctx->b.b.set_constant_buffer = si_set_constant_buffer;
+ sctx->b.b.set_sampler_views = si_set_sampler_views;
+ sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
+ sctx->b.invalidate_buffer = si_invalidate_buffer;
+
+ /* Shader user data. */
+ si_init_atom(sctx, &sctx->shader_userdata.atom, &sctx->atoms.s.shader_userdata,
+ si_emit_shader_userdata);
+
+ /* Set default and immutable mappings. */
+ si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
+ si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
+ si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
+ si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
+}
+
+bool si_upload_shader_descriptors(struct si_context *sctx)
+{
+ int i;
+
+ for (i = 0; i < SI_NUM_SHADERS; i++) {
+ if (!si_upload_descriptors(sctx, &sctx->const_buffers[i].desc) ||
+ !si_upload_descriptors(sctx, &sctx->rw_buffers[i].desc) ||
+ !si_upload_descriptors(sctx, &sctx->samplers[i].views.desc) ||
+ !si_upload_descriptors(sctx, &sctx->images[i].desc))
+ return false;
+ }
+ return si_upload_vertex_buffer_descriptors(sctx);
}
-void si_release_all_descriptors(struct r600_context *rctx)
+void si_release_all_descriptors(struct si_context *sctx)
{
int i;
for (i = 0; i < SI_NUM_SHADERS; i++) {
- si_release_buffer_resources(&rctx->const_buffers[i]);
- si_release_sampler_views(&rctx->samplers[i].views);
+ si_release_buffer_resources(&sctx->const_buffers[i]);
+ si_release_buffer_resources(&sctx->rw_buffers[i]);
+ si_release_sampler_views(&sctx->samplers[i].views);
+ si_release_image_views(&sctx->images[i]);
}
+ si_release_descriptors(&sctx->vertex_buffers);
}
-void si_all_descriptors_begin_new_cs(struct r600_context *rctx)
+void si_all_descriptors_begin_new_cs(struct si_context *sctx)
{
int i;
for (i = 0; i < SI_NUM_SHADERS; i++) {
- si_buffer_resources_begin_new_cs(rctx, &rctx->const_buffers[i]);
- si_sampler_views_begin_new_cs(rctx, &rctx->samplers[i].views);
+ si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
+ si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers[i]);
+ si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
+ si_image_views_begin_new_cs(sctx, &sctx->images[i]);
}
+ si_vertex_buffers_begin_new_cs(sctx);
+ si_shader_userdata_begin_new_cs(sctx);
}
projects / mesa.git / blobdiff