rres = (struct r600_resource*)resource;
priority = si_get_sampler_view_priority(rres);
- radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
- rres, usage, priority,
- check_mem);
+ radeon_add_to_gfx_buffer_list_check_mem(sctx, rres, usage, priority,
+ check_mem);
if (resource->target == PIPE_BUFFER)
return;
/* Now add separate DCC or HTILE. */
rtex = (struct r600_texture*)resource;
if (rtex->dcc_separate_buffer) {
- radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
- rtex->dcc_separate_buffer, usage,
- RADEON_PRIO_DCC, check_mem);
+ radeon_add_to_gfx_buffer_list_check_mem(sctx, rtex->dcc_separate_buffer,
+ usage, RADEON_PRIO_DCC, check_mem);
}
}
if (unlikely(!is_buffer && sview->dcc_incompatible)) {
if (vi_dcc_enabled(rtex, view->u.tex.first_level))
if (!si_texture_disable_dcc(&sctx->b, rtex))
- sctx->b.decompress_dcc(&sctx->b.b, rtex);
+ si_decompress_dcc(&sctx->b.b, rtex);
sview->dcc_incompatible = false;
}
* has been decompressed already.
*/
if (!si_texture_disable_dcc(&ctx->b, tex))
- ctx->b.decompress_dcc(&ctx->b.b, tex);
+ si_decompress_dcc(&ctx->b.b, tex);
}
if (ctx->b.chip_class >= GFX9) {
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
buffers->buffers[slot] = buffer;
- radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
- (struct r600_resource*)buffer,
- buffers->shader_usage_constbuf,
- buffers->priority_constbuf, true);
+ radeon_add_to_gfx_buffer_list_check_mem(sctx,
+ (struct r600_resource*)buffer,
+ buffers->shader_usage_constbuf,
+ buffers->priority_constbuf, true);
buffers->enabled_mask |= 1u << slot;
} else {
/* Clear the descriptor. */
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
- radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx, buf,
- buffers->shader_usage,
- buffers->priority, true);
+ radeon_add_to_gfx_buffer_list_check_mem(sctx, buf,
+ buffers->shader_usage,
+ buffers->priority, true);
buf->bind_history |= PIPE_BIND_SHADER_BUFFER;
buffers->enabled_mask |= 1u << slot;
old_va, buf);
sctx->descriptors_dirty |= 1u << descriptors_idx;
- radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
- (struct r600_resource *)buf,
- usage, priority, true);
+ radeon_add_to_gfx_buffer_list_check_mem(sctx,
+ (struct r600_resource *)buf,
+ usage, priority, true);
}
}
}
-static void si_rebind_buffer(struct pipe_context *ctx, struct pipe_resource *buf,
- uint64_t old_va)
+/* Update all resource bindings where the buffer is bound, including
+ * all resource descriptors. This is invalidate_buffer without
+ * the invalidation. */
+void si_rebind_buffer(struct pipe_context *ctx, struct pipe_resource *buf,
+ uint64_t old_va)
{
struct si_context *sctx = (struct si_context*)ctx;
struct r600_resource *rbuffer = r600_resource(buf);
old_va, buf);
sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
- radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
- rbuffer, buffers->shader_usage,
- RADEON_PRIO_SHADER_RW_BUFFER,
- true);
+ radeon_add_to_gfx_buffer_list_check_mem(sctx,
+ rbuffer, buffers->shader_usage,
+ RADEON_PRIO_SHADER_RW_BUFFER,
+ true);
/* Update the streamout state. */
if (sctx->streamout.begin_emitted)
sctx->descriptors_dirty |=
1u << si_sampler_and_image_descriptors_idx(shader);
- radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
+ radeon_add_to_gfx_buffer_list_check_mem(sctx,
rbuffer, RADEON_USAGE_READ,
RADEON_PRIO_SAMPLER_BUFFER,
true);
sctx->descriptors_dirty |=
1u << si_sampler_and_image_descriptors_idx(shader);
- radeon_add_to_buffer_list_check_mem(
- &sctx->b, &sctx->b.gfx, rbuffer,
+ radeon_add_to_gfx_buffer_list_check_mem(
+ sctx, rbuffer,
RADEON_USAGE_READWRITE,
RADEON_PRIO_SAMPLER_BUFFER, true);
}
(*tex_handle)->desc_dirty = true;
sctx->bindless_descriptors_dirty = true;
- radeon_add_to_buffer_list_check_mem(
- &sctx->b, &sctx->b.gfx, rbuffer,
+ radeon_add_to_gfx_buffer_list_check_mem(
+ sctx, rbuffer,
RADEON_USAGE_READ,
RADEON_PRIO_SAMPLER_BUFFER, true);
}
(*img_handle)->desc_dirty = true;
sctx->bindless_descriptors_dirty = true;
- radeon_add_to_buffer_list_check_mem(
- &sctx->b, &sctx->b.gfx, rbuffer,
+ radeon_add_to_gfx_buffer_list_check_mem(
+ sctx, rbuffer,
RADEON_USAGE_READWRITE,
RADEON_PRIO_SAMPLER_BUFFER, true);
}
}
}
-/* Reallocate a buffer a update all resource bindings where the buffer is
- * bound.
- *
- * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
- * idle by discarding its contents. Apps usually tell us when to do this using
- * map_buffer flags, for example.
- */
-static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
-{
- struct si_context *sctx = (struct si_context*)ctx;
- struct r600_resource *rbuffer = r600_resource(buf);
- uint64_t old_va = rbuffer->gpu_address;
-
- /* Reallocate the buffer in the same pipe_resource. */
- si_alloc_resource(sctx->screen, rbuffer);
-
- si_rebind_buffer(ctx, buf, old_va);
-}
-
static void si_upload_bindless_descriptor(struct si_context *sctx,
unsigned desc_slot,
unsigned num_dwords)
sctx->b.b.create_image_handle = si_create_image_handle;
sctx->b.b.delete_image_handle = si_delete_image_handle;
sctx->b.b.make_image_handle_resident = si_make_image_handle_resident;
- sctx->b.invalidate_buffer = si_invalidate_buffer;
- sctx->b.rebind_buffer = si_rebind_buffer;
/* Shader user data. */
si_init_atom(sctx, &sctx->shader_pointers.atom, &sctx->atoms.s.shader_pointers,