if (sscreen->b.chip_class <= VI)
meta_va += base_level_info->dcc_offset;
- } else if (tex->tc_compatible_htile) {
+ } else if (tex->tc_compatible_htile && first_level == 0) {
meta_va = tex->resource.gpu_address + tex->htile_offset;
}
R_00B330_SPI_SHADER_USER_DATA_ES_0);
si_emit_shader_pointer(sctx, descs,
R_00B430_SPI_SHADER_USER_DATA_HS_0);
+ si_emit_shader_pointer(sctx, descs,
+ R_00B530_SPI_SHADER_USER_DATA_LS_0);
}
}
uint64_t offset)
{
struct r600_resource *buf = r600_resource(resource);
- uint32_t *desc_list = desc->desc_list;
+ uint32_t *desc_list = desc->desc_list + 4;
uint64_t old_desc_va;
assert(resource->target == PIPE_BUFFER);
/* The buffer has been invalidated when the handle wasn't
* resident, update the descriptor and the dirty flag.
*/
- si_set_buf_desc_address(buf, offset, &desc_list[4]);
+ si_set_buf_desc_address(buf, offset, &desc_list[0]);
desc->dirty = true;
sctx->bindless_descriptors_dirty = true;
}
si_release_buffer_resources(&sctx->rw_buffers,
&sctx->descriptors[SI_DESCS_RW_BUFFERS]);
+ for (i = 0; i < SI_NUM_VERTEX_BUFFERS; i++)
+ pipe_vertex_buffer_unreference(&sctx->vertex_buffer[i]);
for (i = 0; i < SI_NUM_DESCS; ++i)
si_release_descriptors(&sctx->descriptors[i]);