radeonsi: silence a Coverity warning
[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
index bd73fcc3f9fc6108a479084b1660b3fd04cb2207..c92a6575ede4b613fe2b2fe58305b3441d4f503d 100644 (file)
@@ -1008,11 +1008,11 @@ static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
 
                if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
                        continue;
-               if (!sctx->vertex_buffer[vb].buffer)
+               if (!sctx->vertex_buffer[vb].buffer.resource)
                        continue;
 
                radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
-                                     (struct r600_resource*)sctx->vertex_buffer[vb].buffer,
+                                     (struct r600_resource*)sctx->vertex_buffer[vb].buffer.resource,
                                      RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
        }
 
@@ -1071,7 +1071,7 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
                uint32_t *desc = &ptr[i*4];
 
                vb = &sctx->vertex_buffer[vbo_index];
-               rbuffer = (struct r600_resource*)vb->buffer;
+               rbuffer = (struct r600_resource*)vb->buffer.resource;
                if (!rbuffer) {
                        memset(desc, 0, 16);
                        continue;
@@ -1087,18 +1087,18 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
 
                if (sctx->b.chip_class != VI && vb->stride) {
                        /* Round up by rounding down and adding 1 */
-                       desc[2] = (vb->buffer->width0 - offset -
+                       desc[2] = (vb->buffer.resource->width0 - offset -
                                   velems->format_size[i]) /
                                  vb->stride + 1;
                } else {
-                       desc[2] = vb->buffer->width0 - offset;
+                       desc[2] = vb->buffer.resource->width0 - offset;
                }
 
                desc[3] = velems->rsrc_word3[i];
 
                if (first_vb_use_mask & (1 << i)) {
                        radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
-                                             (struct r600_resource*)vb->buffer,
+                                             (struct r600_resource*)vb->buffer.resource,
                                              RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
                }
        }
@@ -1626,25 +1626,15 @@ static void si_reset_buffer_resources(struct si_context *sctx,
        }
 }
 
-/* Reallocate a buffer a update all resource bindings where the buffer is
- * bound.
- *
- * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
- * idle by discarding its contents. Apps usually tell us when to do this using
- * map_buffer flags, for example.
- */
-static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
+static void si_rebind_buffer(struct pipe_context *ctx, struct pipe_resource *buf,
+                            uint64_t old_va)
 {
        struct si_context *sctx = (struct si_context*)ctx;
        struct r600_resource *rbuffer = r600_resource(buf);
        unsigned i, shader;
-       uint64_t old_va = rbuffer->gpu_address;
        unsigned num_elems = sctx->vertex_elements ?
                                       sctx->vertex_elements->count : 0;
 
-       /* Reallocate the buffer in the same pipe_resource. */
-       r600_alloc_resource(&sctx->screen->b, rbuffer);
-
        /* We changed the buffer, now we need to bind it where the old one
         * was bound. This consists of 2 things:
         *   1) Updating the resource descriptor and dirtying it.
@@ -1658,10 +1648,10 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
 
                        if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
                                continue;
-                       if (!sctx->vertex_buffer[vb].buffer)
+                       if (!sctx->vertex_buffer[vb].buffer.resource)
                                continue;
 
-                       if (sctx->vertex_buffer[vb].buffer == buf) {
+                       if (sctx->vertex_buffer[vb].buffer.resource == buf) {
                                sctx->vertex_buffers_dirty = true;
                                break;
                        }
@@ -1772,6 +1762,25 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
        }
 }
 
+/* Reallocate a buffer a update all resource bindings where the buffer is
+ * bound.
+ *
+ * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
+ * idle by discarding its contents. Apps usually tell us when to do this using
+ * map_buffer flags, for example.
+ */
+static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
+{
+       struct si_context *sctx = (struct si_context*)ctx;
+       struct r600_resource *rbuffer = r600_resource(buf);
+       uint64_t old_va = rbuffer->gpu_address;
+
+       /* Reallocate the buffer in the same pipe_resource. */
+       r600_alloc_resource(&sctx->screen->b, rbuffer);
+
+       si_rebind_buffer(ctx, buf, old_va);
+}
+
 /* Update mutable image descriptor fields of all bound textures. */
 void si_update_all_texture_descriptors(struct si_context *sctx)
 {
@@ -1926,16 +1935,21 @@ void si_emit_graphics_shader_userdata(struct si_context *sctx,
                                       R_00B030_SPI_SHADER_USER_DATA_PS_0);
                si_emit_shader_pointer(sctx, descs,
                                       R_00B130_SPI_SHADER_USER_DATA_VS_0);
-               si_emit_shader_pointer(sctx, descs,
-                                      R_00B330_SPI_SHADER_USER_DATA_ES_0);
 
-               /* GFX9 merged LS-HS and ES-GS. Only set RW_BUFFERS for ES and LS. */
                if (sctx->b.chip_class >= GFX9) {
+                       /* GFX9 merged LS-HS and ES-GS.
+                        * Set RW_BUFFERS in the special registers, so that
+                        * it's preloaded into s[0:1] instead of s[8:9].
+                        */
+                       si_emit_shader_pointer(sctx, descs,
+                                              R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS);
                        si_emit_shader_pointer(sctx, descs,
-                                              R_00B430_SPI_SHADER_USER_DATA_LS_0);
+                                              R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS);
                } else {
                        si_emit_shader_pointer(sctx, descs,
                                               R_00B230_SPI_SHADER_USER_DATA_GS_0);
+                       si_emit_shader_pointer(sctx, descs,
+                                              R_00B330_SPI_SHADER_USER_DATA_ES_0);
                        si_emit_shader_pointer(sctx, descs,
                                               R_00B430_SPI_SHADER_USER_DATA_HS_0);
                }
@@ -1986,7 +2000,14 @@ void si_init_all_descriptors(struct si_context *sctx)
        int i;
        unsigned ce_offset = 0;
 
+       STATIC_ASSERT(GFX9_SGPR_TCS_CONST_BUFFERS % 2 == 0);
+       STATIC_ASSERT(GFX9_SGPR_GS_CONST_BUFFERS % 2 == 0);
+
        for (i = 0; i < SI_NUM_SHADERS; i++) {
+               bool gfx9_tcs = sctx->b.chip_class == GFX9 &&
+                               i == PIPE_SHADER_TESS_CTRL;
+               bool gfx9_gs = sctx->b.chip_class == GFX9 &&
+                              i == PIPE_SHADER_GEOMETRY;
                /* GFX9 has only 4KB of CE, while previous chips had 32KB.
                 * Rarely used descriptors don't use CE RAM.
                 */
@@ -1999,22 +2020,34 @@ void si_init_all_descriptors(struct si_context *sctx)
 
                si_init_buffer_resources(&sctx->const_buffers[i],
                                         si_const_buffer_descriptors(sctx, i),
-                                        SI_NUM_CONST_BUFFERS, SI_SGPR_CONST_BUFFERS,
+                                        SI_NUM_CONST_BUFFERS,
+                                        gfx9_tcs ? GFX9_SGPR_TCS_CONST_BUFFERS :
+                                        gfx9_gs ? GFX9_SGPR_GS_CONST_BUFFERS :
+                                                  SI_SGPR_CONST_BUFFERS,
                                         RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER,
                                         &ce_offset);
                si_init_buffer_resources(&sctx->shader_buffers[i],
                                         si_shader_buffer_descriptors(sctx, i),
-                                        SI_NUM_SHADER_BUFFERS, SI_SGPR_SHADER_BUFFERS,
+                                        SI_NUM_SHADER_BUFFERS,
+                                        gfx9_tcs ? GFX9_SGPR_TCS_SHADER_BUFFERS :
+                                        gfx9_gs ? GFX9_SGPR_GS_SHADER_BUFFERS :
+                                                  SI_SGPR_SHADER_BUFFERS,
                                         RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RW_BUFFER,
                                         shaderbufs_use_ce ? &ce_offset : NULL);
 
                si_init_descriptors(si_sampler_descriptors(sctx, i),
-                                   SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS,
+                                   gfx9_tcs ? GFX9_SGPR_TCS_SAMPLERS :
+                                   gfx9_gs ? GFX9_SGPR_GS_SAMPLERS :
+                                             SI_SGPR_SAMPLERS,
+                                   16, SI_NUM_SAMPLERS,
                                    null_texture_descriptor,
                                    samplers_use_ce ? &ce_offset : NULL);
 
                si_init_descriptors(si_image_descriptors(sctx, i),
-                                   SI_SGPR_IMAGES, 8, SI_NUM_IMAGES,
+                                   gfx9_tcs ? GFX9_SGPR_TCS_IMAGES :
+                                   gfx9_gs ? GFX9_SGPR_GS_IMAGES :
+                                             SI_SGPR_IMAGES,
+                                   8, SI_NUM_IMAGES,
                                    null_image_descriptor,
                                    images_use_ce ? &ce_offset : NULL);
        }
@@ -2043,6 +2076,7 @@ void si_init_all_descriptors(struct si_context *sctx)
        sctx->b.b.set_sampler_views = si_set_sampler_views;
        sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
        sctx->b.invalidate_buffer = si_invalidate_buffer;
+       sctx->b.rebind_buffer = si_rebind_buffer;
 
        /* Shader user data. */
        si_init_atom(sctx, &sctx->shader_userdata.atom, &sctx->atoms.s.shader_userdata,