desc->buffer = (struct r600_resource*)
pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
- PIPE_USAGE_STATIC,
+ PIPE_USAGE_DEFAULT,
SI_NUM_CONTEXTS * desc->context_size);
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, desc->buffer, RADEON_USAGE_READWRITE);
7 + /* copy */
(4 + desc->element_dw_size) * util_bitcount(desc->dirty_mask) + /* update */
4; /* pointer update */
+#if HAVE_LLVM >= 0x0305
+ if (desc->shader_userdata_reg >= R_00B130_SPI_SHADER_USER_DATA_VS_0 &&
+ desc->shader_userdata_reg < R_00B230_SPI_SHADER_USER_DATA_GS_0)
+ desc->atom.num_dw += 4; /* second pointer update */
+#endif
desc->atom.dirty = true;
/* The descriptors are read with the K cache. */
sctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
radeon_emit(cs, (desc->shader_userdata_reg - SI_SH_REG_OFFSET) >> 2);
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
+
+#if HAVE_LLVM >= 0x0305
+ if (desc->shader_userdata_reg >= R_00B130_SPI_SHADER_USER_DATA_VS_0 &&
+ desc->shader_userdata_reg < R_00B230_SPI_SHADER_USER_DATA_GS_0) {
+ radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
+ radeon_emit(cs, (desc->shader_userdata_reg +
+ (R_00B330_SPI_SHADER_USER_DATA_ES_0 -
+ R_00B130_SPI_SHADER_USER_DATA_VS_0) -
+ SI_SH_REG_OFFSET) >> 2);
+ radeon_emit(cs, va);
+ radeon_emit(cs, va >> 32);
+ }
+#endif
}
static void si_emit_descriptors(struct si_context *sctx,
static unsigned si_get_shader_user_data_base(unsigned shader)
{
switch (shader) {
- case SI_SHADER_EXPORT:
- return R_00B330_SPI_SHADER_USER_DATA_ES_0;
case PIPE_SHADER_VERTEX:
return R_00B130_SPI_SHADER_USER_DATA_VS_0;
case PIPE_SHADER_GEOMETRY:
unsigned element_size, unsigned index_stride)
{
struct si_context *sctx = (struct si_context *)ctx;
- struct si_buffer_resources *buffers = &sctx->const_buffers[shader];
+ struct si_buffer_resources *buffers = &sctx->rw_buffers[shader];
if (shader >= SI_NUM_SHADERS)
return;
/* The stride field in the resource descriptor has 14 bits */
assert(stride < (1 << 14));
- slot += NUM_PIPE_CONST_BUFFERS + 1;
assert(slot < buffers->num_buffers);
pipe_resource_reference(&buffers->buffers[slot], NULL);
unsigned append_bitmask)
{
struct si_context *sctx = (struct si_context *)ctx;
- struct si_buffer_resources *buffers = &sctx->streamout_buffers;
+ struct si_buffer_resources *buffers = &sctx->rw_buffers[PIPE_SHADER_VERTEX];
unsigned old_num_targets = sctx->b.streamout.num_targets;
- unsigned i;
+ unsigned i, bufidx;
/* Streamout buffers must be bound in 2 places:
* 1) in VGT by setting the VGT_STRMOUT registers
/* Set the shader resources.*/
for (i = 0; i < num_targets; i++) {
+ bufidx = SI_RW_SO + i;
+
if (targets[i]) {
struct pipe_resource *buffer = targets[i]->buffer;
uint64_t va = r600_resource_va(ctx->screen, buffer);
/* Set the descriptor. */
- uint32_t *desc = buffers->desc_data[i];
+ uint32_t *desc = buffers->desc_data[bufidx];
desc[0] = va;
desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
desc[2] = 0xffffffff;
S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
/* Set the resource. */
- pipe_resource_reference(&buffers->buffers[i], buffer);
+ pipe_resource_reference(&buffers->buffers[bufidx],
+ buffer);
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
(struct r600_resource*)buffer,
buffers->shader_usage);
- buffers->desc.enabled_mask |= 1 << i;
+ buffers->desc.enabled_mask |= 1 << bufidx;
} else {
/* Clear the descriptor and unset the resource. */
- memset(buffers->desc_data[i], 0, sizeof(uint32_t) * 4);
- pipe_resource_reference(&buffers->buffers[i], NULL);
- buffers->desc.enabled_mask &= ~(1 << i);
+ memset(buffers->desc_data[bufidx], 0,
+ sizeof(uint32_t) * 4);
+ pipe_resource_reference(&buffers->buffers[bufidx],
+ NULL);
+ buffers->desc.enabled_mask &= ~(1 << bufidx);
}
- buffers->desc.dirty_mask |= 1 << i;
+ buffers->desc.dirty_mask |= 1 << bufidx;
}
for (; i < old_num_targets; i++) {
+ bufidx = SI_RW_SO + i;
/* Clear the descriptor and unset the resource. */
- memset(buffers->desc_data[i], 0, sizeof(uint32_t) * 4);
- pipe_resource_reference(&buffers->buffers[i], NULL);
- buffers->desc.enabled_mask &= ~(1 << i);
- buffers->desc.dirty_mask |= 1 << i;
+ memset(buffers->desc_data[bufidx], 0, sizeof(uint32_t) * 4);
+ pipe_resource_reference(&buffers->buffers[bufidx], NULL);
+ buffers->desc.enabled_mask &= ~(1 << bufidx);
+ buffers->desc.dirty_mask |= 1 << bufidx;
}
si_update_descriptors(sctx, &buffers->desc);
pb_reference(&rbuffer->buf, NULL);
/* Create a new one in the same pipe_resource. */
- r600_init_resource(&sctx->screen->b, rbuffer, rbuffer->b.b.width0, alignment,
- TRUE, rbuffer->b.b.usage);
+ r600_init_resource(&sctx->screen->b, rbuffer, rbuffer->b.b.width0,
+ alignment, TRUE);
/* We changed the buffer, now we need to bind it where the old one
* was bound. This consists of 2 things:
/* Vertex buffers. */
/* Nothing to do. Vertex buffer bindings are updated before every draw call. */
- /* Streamout buffers. */
- for (i = 0; i < sctx->streamout_buffers.num_buffers; i++) {
- if (sctx->streamout_buffers.buffers[i] == buf) {
- /* Update the descriptor. */
- si_desc_reset_buffer_offset(ctx, sctx->streamout_buffers.desc_data[i],
- old_va, buf);
+ /* Read/Write buffers. */
+ for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
+ struct si_buffer_resources *buffers = &sctx->rw_buffers[shader];
+ bool found = false;
+ uint32_t mask = buffers->desc.enabled_mask;
- r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
- (struct r600_resource*)buf,
- sctx->streamout_buffers.shader_usage);
- sctx->streamout_buffers.desc.dirty_mask |= 1 << i;
- si_update_descriptors(sctx, &sctx->streamout_buffers.desc);
-
- /* Update the streamout state. */
- if (sctx->b.streamout.begin_emitted) {
- r600_emit_streamout_end(&sctx->b);
+ while (mask) {
+ i = u_bit_scan(&mask);
+ if (buffers->buffers[i] == buf) {
+ si_desc_reset_buffer_offset(ctx, buffers->desc_data[i],
+ old_va, buf);
+
+ r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+ rbuffer, buffers->shader_usage);
+
+ buffers->desc.dirty_mask |= 1 << i;
+ found = true;
+
+ if (i >= SI_RW_SO && shader == PIPE_SHADER_VERTEX) {
+ /* Update the streamout state. */
+ if (sctx->b.streamout.begin_emitted) {
+ r600_emit_streamout_end(&sctx->b);
+ }
+ sctx->b.streamout.append_bitmask =
+ sctx->b.streamout.enabled_mask;
+ r600_streamout_buffers_dirty(&sctx->b);
+ }
}
- sctx->b.streamout.append_bitmask = sctx->b.streamout.enabled_mask;
- r600_streamout_buffers_dirty(&sctx->b);
+ }
+ if (found) {
+ si_update_descriptors(sctx, &buffers->desc);
}
}
for (i = 0; i < SI_NUM_SHADERS; i++) {
si_init_buffer_resources(sctx, &sctx->const_buffers[i],
NUM_CONST_BUFFERS, i, SI_SGPR_CONST,
+ RADEON_USAGE_READ);
+ si_init_buffer_resources(sctx, &sctx->rw_buffers[i],
+ i == PIPE_SHADER_VERTEX ?
+ SI_RW_SO + 4 : SI_RW_SO,
+ i, SI_SGPR_RW_BUFFERS,
RADEON_USAGE_READWRITE);
si_init_sampler_views(sctx, &sctx->samplers[i].views, i);
sctx->atoms.const_buffers[i] = &sctx->const_buffers[i].desc.atom;
+ sctx->atoms.rw_buffers[i] = &sctx->rw_buffers[i].desc.atom;
sctx->atoms.sampler_views[i] = &sctx->samplers[i].views.desc.atom;
}
- si_init_buffer_resources(sctx, &sctx->streamout_buffers, 4, PIPE_SHADER_VERTEX,
- SI_SGPR_SO_BUFFER, RADEON_USAGE_WRITE);
- sctx->atoms.streamout_buffers = &sctx->streamout_buffers.desc.atom;
/* Set pipe_context functions. */
sctx->b.b.set_constant_buffer = si_set_constant_buffer;
for (i = 0; i < SI_NUM_SHADERS; i++) {
si_release_buffer_resources(&sctx->const_buffers[i]);
+ si_release_buffer_resources(&sctx->rw_buffers[i]);
si_release_sampler_views(&sctx->samplers[i].views);
}
- si_release_buffer_resources(&sctx->streamout_buffers);
}
void si_all_descriptors_begin_new_cs(struct si_context *sctx)
for (i = 0; i < SI_NUM_SHADERS; i++) {
si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
+ si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers[i]);
si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
}
- si_buffer_resources_begin_new_cs(sctx, &sctx->streamout_buffers);
}
projects / mesa.git / blobdiff