* Sampler states are never unbound except when FMASK is bound.
*/
-#include "radeon/r600_cs.h"
#include "si_pipe.h"
#include "sid.h"
#include "gfx9d.h"
* descriptor */
};
-static uint64_t si_desc_extract_buffer_address(uint32_t *desc)
+static uint64_t si_desc_extract_buffer_address(const uint32_t *desc)
{
uint64_t va = desc[0] |
((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
r600_resource_reference(&desc->buffer, NULL);
desc->gpu_list = NULL;
desc->gpu_address = si_desc_extract_buffer_address(descriptor);
- si_mark_atom_dirty(sctx, &sctx->shader_pointers.atom);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
return true;
}
uint32_t *ptr;
unsigned buffer_offset;
- u_upload_alloc(sctx->b.b.const_uploader, first_slot_offset, upload_size,
+ u_upload_alloc(sctx->b.const_uploader, first_slot_offset, upload_size,
si_optimal_tcc_alignment(sctx, upload_size),
&buffer_offset, (struct pipe_resource**)&desc->buffer,
(void**)&ptr);
upload_size);
desc->gpu_list = ptr - first_slot_offset / 4;
- radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs, desc->buffer,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs, desc->buffer,
RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
/* The shader pointer should point to slot 0. */
assert((desc->buffer->gpu_address >> 32) == sctx->screen->info.address32_hi);
assert((desc->gpu_address >> 32) == sctx->screen->info.address32_hi);
- si_mark_atom_dirty(sctx, &sctx->shader_pointers.atom);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
return true;
}
if (!desc->buffer)
return;
- radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs, desc->buffer,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs, desc->buffer,
RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
}
struct r600_texture *tex = (struct r600_texture*)resource;
if (tex->is_depth && !si_can_sample_zs(tex, is_stencil_sampler))
- resource = &tex->flushed_depth_texture->resource.b.b;
+ resource = &tex->flushed_depth_texture->buffer.b.b;
}
- rres = (struct r600_resource*)resource;
+ rres = r600_resource(resource);
priority = si_get_sampler_view_priority(rres);
radeon_add_to_gfx_buffer_list_check_mem(sctx, rres, usage, priority,
is_stencil = false;
}
- va = tex->resource.gpu_address;
+ va = tex->buffer.gpu_address;
if (sscreen->info.chip_class >= GFX9) {
/* Only stencil_offset needs to be added here. */
state[7] = 0;
if (vi_dcc_enabled(tex, first_level)) {
- meta_va = (!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
+ meta_va = (!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
tex->dcc_offset;
if (sscreen->info.chip_class == VI) {
meta_va |= (uint32_t)tex->surface.tile_swizzle << 8;
} else if (vi_tc_compat_htile_enabled(tex, first_level)) {
- meta_va = tex->resource.gpu_address + tex->htile_offset;
+ meta_va = tex->buffer.gpu_address + tex->htile_offset;
}
if (meta_va) {
{
struct pipe_sampler_view *view = &sview->base;
struct r600_texture *rtex = (struct r600_texture *)view->texture;
- bool is_buffer = rtex->resource.b.b.target == PIPE_BUFFER;
+ bool is_buffer = rtex->buffer.b.b.target == PIPE_BUFFER;
if (unlikely(!is_buffer && sview->dcc_incompatible)) {
if (vi_dcc_enabled(rtex, view->u.tex.first_level))
if (!si_texture_disable_dcc(sctx, rtex))
- si_decompress_dcc(&sctx->b.b, rtex);
+ si_decompress_dcc(sctx, rtex);
sview->dcc_incompatible = false;
}
memcpy(desc, sview->state, 8*4);
if (is_buffer) {
- si_set_buf_desc_address(&rtex->resource,
+ si_set_buf_desc_address(&rtex->buffer,
sview->base.u.buf.offset,
desc + 4);
} else {
desc);
}
- if (!is_buffer && rtex->fmask.size) {
+ if (!is_buffer && rtex->surface.fmask_size) {
memcpy(desc + 8, sview->fmask_state, 8*4);
} else {
/* Disable FMASK and bind sampler state in [12:15]. */
static bool color_needs_decompression(struct r600_texture *rtex)
{
- return rtex->fmask.size ||
+ return rtex->surface.fmask_size ||
(rtex->dirty_level_mask &&
(rtex->cmask.size || rtex->dcc_offset));
}
si_set_sampler_view_desc(sctx, rview,
samplers->sampler_states[slot], desc);
- if (rtex->resource.b.b.target == PIPE_BUFFER) {
- rtex->resource.bind_history |= PIPE_BIND_SAMPLER_VIEW;
+ if (rtex->buffer.b.b.target == PIPE_BUFFER) {
+ rtex->buffer.bind_history |= PIPE_BIND_SAMPLER_VIEW;
samplers->needs_depth_decompress_mask &= ~(1u << slot);
samplers->needs_color_decompress_mask &= ~(1u << slot);
} else {
static void
si_mark_image_range_valid(const struct pipe_image_view *view)
{
- struct r600_resource *res = (struct r600_resource *)view->resource;
+ struct r600_resource *res = r600_resource(view->resource);
assert(res && res->b.b.target == PIPE_BUFFER);
struct si_screen *screen = ctx->screen;
struct r600_resource *res;
- res = (struct r600_resource *)view->resource;
+ res = r600_resource(view->resource);
if (res->b.b.target == PIPE_BUFFER) {
if (view->access & PIPE_IMAGE_ACCESS_WRITE)
* so we don't wanna trigger it.
*/
if (tex->is_depth ||
- (!fmask_desc && tex->fmask.size != 0)) {
+ (!fmask_desc && tex->surface.fmask_size != 0)) {
assert(!"Z/S and MSAA image stores are not supported");
access &= ~PIPE_IMAGE_ACCESS_WRITE;
}
assert(!tex->is_depth);
- assert(fmask_desc || tex->fmask.size == 0);
+ assert(fmask_desc || tex->surface.fmask_size == 0);
if (uses_dcc && !skip_decompress &&
(view->access & PIPE_IMAGE_ACCESS_WRITE ||
* has been decompressed already.
*/
if (!si_texture_disable_dcc(ctx, tex))
- si_decompress_dcc(&ctx->b.b, tex);
+ si_decompress_dcc(ctx, tex);
}
- if (ctx->b.chip_class >= GFX9) {
+ if (ctx->chip_class >= GFX9) {
/* Always set the base address. The swizzle modes don't
* allow setting mipmap level offsets as the base.
*/
return;
}
- res = (struct r600_resource *)view->resource;
+ res = r600_resource(view->resource);
if (&images->views[slot] != view)
util_copy_image_view(&images->views[slot], view);
*/
si_texture_disable_dcc(sctx, tex);
- if (tex->resource.b.b.nr_samples <= 1 && tex->cmask_buffer) {
+ if (tex->buffer.b.b.nr_samples <= 1 && tex->cmask_buffer) {
/* Disable CMASK. */
- assert(tex->cmask_buffer != &tex->resource);
+ assert(tex->cmask_buffer != &tex->buffer);
si_eliminate_fast_color_clear(sctx, tex);
si_texture_discard_cmask(sctx->screen, tex);
}
memset(desc, 0, 16 * 4);
si_set_shader_image_desc(sctx, &view, true, desc, desc + 8);
- pipe_resource_reference(&buffers->buffers[slot], &tex->resource.b.b);
- radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
- &tex->resource, RADEON_USAGE_READ,
+ pipe_resource_reference(&buffers->buffers[slot], &tex->buffer.b.b);
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
+ &tex->buffer, RADEON_USAGE_READ,
RADEON_PRIO_SHADER_RW_IMAGE);
buffers->enabled_mask |= 1u << slot;
} else {
sview->base.texture->target != PIPE_BUFFER)
tex = (struct r600_texture *)sview->base.texture;
- if (tex && tex->fmask.size)
+ if (tex && tex->surface.fmask_size)
continue;
si_set_sampler_state_desc(sstates[i], sview, tex,
while (mask) {
int i = u_bit_scan(&mask);
- radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
r600_resource(buffers->buffers[i]),
i < SI_NUM_SHADER_BUFFERS ? buffers->shader_usage :
buffers->shader_usage_constbuf,
*size = desc[2];
assert(G_008F04_STRIDE(desc[1]) == 0);
- va = ((uint64_t)desc[1] << 32) | desc[0];
+ va = si_desc_extract_buffer_address(desc);
assert(va >= res->gpu_address && va + *size <= res->gpu_address + res->bo_size);
*offset = va - res->gpu_address;
if (!sctx->vertex_buffer[vb].buffer.resource)
continue;
- radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
- (struct r600_resource*)sctx->vertex_buffer[vb].buffer.resource,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
+ r600_resource(sctx->vertex_buffer[vb].buffer.resource),
RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
}
if (!sctx->vb_descriptors_buffer)
return;
- radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
sctx->vb_descriptors_buffer, RADEON_USAGE_READ,
RADEON_PRIO_DESCRIPTORS);
}
* directly through a staging buffer and don't go through
* the fine-grained upload path.
*/
- u_upload_alloc(sctx->b.b.const_uploader, 0,
+ u_upload_alloc(sctx->b.const_uploader, 0,
desc_list_byte_size,
si_optimal_tcc_alignment(sctx, desc_list_byte_size),
&sctx->vb_descriptors_offset,
}
sctx->vb_descriptors_gpu_list = ptr;
- radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
sctx->vb_descriptors_buffer, RADEON_USAGE_READ,
RADEON_PRIO_DESCRIPTORS);
uint32_t *desc = &ptr[i*4];
vb = &sctx->vertex_buffer[vbo_index];
- rbuffer = (struct r600_resource*)vb->buffer.resource;
+ rbuffer = r600_resource(vb->buffer.resource);
if (!rbuffer) {
memset(desc, 0, 16);
continue;
uint64_t va = rbuffer->gpu_address + offset;
int64_t num_records = (int64_t)rbuffer->b.b.width0 - offset;
- if (sctx->b.chip_class != VI && vb->stride) {
+ if (sctx->chip_class != VI && vb->stride) {
/* Round up by rounding down and adding 1 */
num_records = (num_records - velems->format_size[i]) /
vb->stride + 1;
desc[3] = velems->rsrc_word3[i];
if (first_vb_use_mask & (1 << i)) {
- radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
- (struct r600_resource*)vb->buffer.resource,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
+ r600_resource(vb->buffer.resource),
RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
}
}
* on performance (confirmed by testing). New descriptors are always
* uploaded to a fresh new buffer, so I don't think flushing the const
* cache is needed. */
- si_mark_atom_dirty(sctx, &sctx->shader_pointers.atom);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
sctx->vertex_buffers_dirty = false;
sctx->vertex_buffer_pointer_dirty = true;
sctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
{
void *tmp;
- u_upload_alloc(sctx->b.b.const_uploader, 0, size,
+ u_upload_alloc(sctx->b.const_uploader, 0, size,
si_optimal_tcc_alignment(sctx, size),
const_offset,
(struct pipe_resource**)rbuffer, &tmp);
/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
* with a NULL buffer). We need to use a dummy buffer instead. */
- if (sctx->b.chip_class == CIK &&
+ if (sctx->chip_class == CIK &&
(!input || (!input->buffer && !input->user_buffer)))
input = &sctx->null_const_buf;
buffers->buffers[slot] = buffer;
radeon_add_to_gfx_buffer_list_check_mem(sctx,
- (struct r600_resource*)buffer,
+ r600_resource(buffer),
buffers->shader_usage_constbuf,
buffers->priority_constbuf, true);
buffers->enabled_mask |= 1u << slot;
continue;
}
- buf = (struct r600_resource *)sbuffer->buffer;
+ buf = r600_resource(sbuffer->buffer);
va = buf->gpu_address + sbuffer->buffer_offset;
desc[0] = va;
/* RING BUFFERS */
-void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
+void si_set_ring_buffer(struct si_context *sctx, uint slot,
struct pipe_resource *buffer,
unsigned stride, unsigned num_records,
bool add_tid, bool swizzle,
unsigned element_size, unsigned index_stride, uint64_t offset)
{
- struct si_context *sctx = (struct si_context *)ctx;
struct si_buffer_resources *buffers = &sctx->rw_buffers;
struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
break;
}
- if (sctx->b.chip_class >= VI && stride)
+ if (sctx->chip_class >= VI && stride)
num_records *= stride;
/* Set the descriptor. */
S_008F0C_INDEX_STRIDE(index_stride) |
S_008F0C_ADD_TID_ENABLE(add_tid);
- if (sctx->b.chip_class >= GFX9)
+ if (sctx->chip_class >= GFX9)
assert(!swizzle || element_size == 1); /* always 4 bytes on GFX9 */
else
desc[3] |= S_008F0C_ELEMENT_SIZE(element_size);
pipe_resource_reference(&buffers->buffers[slot], buffer);
- radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
- (struct r600_resource*)buffer,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
+ r600_resource(buffer),
buffers->shader_usage, buffers->priority);
buffers->enabled_mask |= 1u << slot;
} else {
sctx->descriptors_dirty |= 1u << descriptors_idx;
radeon_add_to_gfx_buffer_list_check_mem(sctx,
- (struct r600_resource *)buf,
+ r600_resource(buf),
usage, priority, true);
}
}
unsigned num_dwords)
{
struct si_descriptors *desc = &sctx->bindless_descriptors;
- struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
unsigned desc_slot_offset = desc_slot * 16;
uint32_t *data;
uint64_t va;
/* Wait for graphics/compute to be idle before updating the resident
* descriptors directly in memory, in case the GPU is using them.
*/
- sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
+ sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
SI_CONTEXT_CS_PARTIAL_FLUSH;
si_emit_cache_flush(sctx);
}
/* Invalidate L1 because it doesn't know that L2 changed. */
- sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1;
+ sctx->flags |= SI_CONTEXT_INV_SMEM_L1;
si_emit_cache_flush(sctx);
sctx->bindless_descriptors_dirty = false;
if (shader == PIPE_SHADER_VERTEX)
sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
- si_mark_atom_dirty(sctx, &sctx->shader_pointers.atom);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
}
static void si_shader_pointers_begin_new_cs(struct si_context *sctx)
{
sctx->shader_pointers_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
- si_mark_atom_dirty(sctx, &sctx->shader_pointers.atom);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
sctx->graphics_bindless_pointer_dirty = sctx->bindless_descriptors.buffer != NULL;
sctx->compute_bindless_pointer_dirty = sctx->bindless_descriptors.buffer != NULL;
}
{
/* VS can be bound as VS, ES, or LS. */
if (sctx->tes_shader.cso) {
- if (sctx->b.chip_class >= GFX9) {
+ if (sctx->chip_class >= GFX9) {
si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
R_00B430_SPI_SHADER_USER_DATA_LS_0);
} else {
}
}
-static void si_emit_shader_pointer_head(struct radeon_winsys_cs *cs,
+static void si_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
unsigned sh_offset,
unsigned pointer_count)
{
}
static void si_emit_shader_pointer_body(struct si_screen *sscreen,
- struct radeon_winsys_cs *cs,
+ struct radeon_cmdbuf *cs,
uint64_t va)
{
radeon_emit(cs, va);
struct si_descriptors *desc,
unsigned sh_base)
{
- struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
unsigned sh_offset = sh_base + desc->shader_userdata_offset;
si_emit_shader_pointer_head(cs, sh_offset, 1);
if (!sh_base)
return;
- struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
unsigned mask = sctx->shader_pointers_dirty & pointer_mask;
while (mask) {
if (!sh_base)
return;
- struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
unsigned mask = sctx->shader_pointers_dirty & pointer_mask;
while (mask) {
static void si_emit_global_shader_pointers(struct si_context *sctx,
struct si_descriptors *descs)
{
- if (sctx->b.chip_class == GFX9) {
+ if (sctx->chip_class == GFX9) {
/* Broadcast it to all shader stages. */
si_emit_shader_pointer(sctx, descs,
R_00B530_SPI_SHADER_USER_DATA_COMMON_0);
R_00B530_SPI_SHADER_USER_DATA_LS_0);
}
-void si_emit_graphics_shader_pointers(struct si_context *sctx,
- struct r600_atom *atom)
+void si_emit_graphics_shader_pointers(struct si_context *sctx)
{
uint32_t *sh_base = sctx->shader_pointers.sh_base;
sh_base[PIPE_SHADER_TESS_EVAL]);
si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(FRAGMENT),
sh_base[PIPE_SHADER_FRAGMENT]);
- if (HAVE_32BIT_POINTERS || sctx->b.chip_class <= VI) {
+ if (HAVE_32BIT_POINTERS || sctx->chip_class <= VI) {
si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(TESS_CTRL),
sh_base[PIPE_SHADER_TESS_CTRL]);
si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(GEOMETRY),
~u_bit_consecutive(SI_DESCS_RW_BUFFERS, SI_DESCS_FIRST_COMPUTE);
if (sctx->vertex_buffer_pointer_dirty) {
- struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
/* Find the location of the VB descriptor pointer. */
/* TODO: In the future, the pointer will be packed in unused
* bits of the first 2 VB descriptors. */
unsigned sh_dw_offset = SI_VS_NUM_USER_SGPR;
- if (sctx->b.chip_class >= GFX9) {
+ if (sctx->chip_class >= GFX9) {
if (sctx->tes_shader.cso)
sh_dw_offset = GFX9_TCS_NUM_USER_SGPR;
else if (sctx->gs_shader.cso)
img_handle = (struct si_image_handle *)entry->data;
view = &img_handle->view;
- res = (struct r600_resource *)view->resource;
+ res = r600_resource(view->resource);
if (resident) {
if (res->b.b.target != PIPE_BUFFER) {
false, false);
}
- sctx->b.num_resident_handles += num_resident_tex_handles +
+ sctx->num_resident_handles += num_resident_tex_handles +
num_resident_img_handles;
}
#endif
for (i = 0; i < SI_NUM_SHADERS; i++) {
- bool is_2nd = sctx->b.chip_class >= GFX9 &&
+ bool is_2nd = sctx->chip_class >= GFX9 &&
(i == PIPE_SHADER_TESS_CTRL ||
i == PIPE_SHADER_GEOMETRY);
unsigned num_sampler_slots = SI_NUM_IMAGES / 2 + SI_NUM_SAMPLERS;
sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
/* Set pipe_context functions. */
- sctx->b.b.bind_sampler_states = si_bind_sampler_states;
- sctx->b.b.set_shader_images = si_set_shader_images;
- sctx->b.b.set_constant_buffer = si_pipe_set_constant_buffer;
- sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
- sctx->b.b.set_shader_buffers = si_set_shader_buffers;
- sctx->b.b.set_sampler_views = si_set_sampler_views;
- sctx->b.b.create_texture_handle = si_create_texture_handle;
- sctx->b.b.delete_texture_handle = si_delete_texture_handle;
- sctx->b.b.make_texture_handle_resident = si_make_texture_handle_resident;
- sctx->b.b.create_image_handle = si_create_image_handle;
- sctx->b.b.delete_image_handle = si_delete_image_handle;
- sctx->b.b.make_image_handle_resident = si_make_image_handle_resident;
+ sctx->b.bind_sampler_states = si_bind_sampler_states;
+ sctx->b.set_shader_images = si_set_shader_images;
+ sctx->b.set_constant_buffer = si_pipe_set_constant_buffer;
+ sctx->b.set_polygon_stipple = si_set_polygon_stipple;
+ sctx->b.set_shader_buffers = si_set_shader_buffers;
+ sctx->b.set_sampler_views = si_set_sampler_views;
+ sctx->b.create_texture_handle = si_create_texture_handle;
+ sctx->b.delete_texture_handle = si_delete_texture_handle;
+ sctx->b.make_texture_handle_resident = si_make_texture_handle_resident;
+ sctx->b.create_image_handle = si_create_image_handle;
+ sctx->b.delete_image_handle = si_delete_image_handle;
+ sctx->b.make_image_handle_resident = si_make_image_handle_resident;
/* Shader user data. */
- si_init_atom(sctx, &sctx->shader_pointers.atom, &sctx->atoms.s.shader_pointers,
- si_emit_graphics_shader_pointers);
+ sctx->atoms.s.shader_pointers.emit = si_emit_graphics_shader_pointers;
/* Set default and immutable mappings. */
si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
- if (sctx->b.chip_class >= GFX9) {
+ if (sctx->chip_class >= GFX9) {
si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL,
R_00B430_SPI_SHADER_USER_DATA_LS_0);
si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY,
projects / mesa.git / blobdiff