/*
* Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Jerome Glisse
*/
#include "sid.h"
uint64_t src_offset,
uint64_t size)
{
- struct radeon_winsys_cs *cs = ctx->b.dma.cs;
+ struct radeon_winsys_cs *cs = ctx->dma_cs;
unsigned i, ncopy, count, max_size, sub_cmd, shift;
- struct r600_resource *rdst = (struct r600_resource*)dst;
- struct r600_resource *rsrc = (struct r600_resource*)src;
+ struct r600_resource *rdst = r600_resource(dst);
+ struct r600_resource *rsrc = r600_resource(src);
/* Mark the buffer range of destination as valid (initialized),
* so that transfer_map knows it should wait for the GPU when mapping
}
ncopy = DIV_ROUND_UP(size, max_size);
- si_need_dma_space(&ctx->b, ncopy * 5, rdst, rsrc);
+ si_need_dma_space(ctx, ncopy * 5, rdst, rsrc);
for (i = 0; i < ncopy; i++) {
count = MIN2(size, max_size);
}
}
-static void si_dma_clear_buffer(struct pipe_context *ctx,
+static void si_dma_clear_buffer(struct si_context *sctx,
struct pipe_resource *dst,
uint64_t offset,
uint64_t size,
unsigned clear_value)
{
- struct si_context *sctx = (struct si_context *)ctx;
- struct radeon_winsys_cs *cs = sctx->b.dma.cs;
+ struct radeon_winsys_cs *cs = sctx->dma_cs;
unsigned i, ncopy, csize;
struct r600_resource *rdst = r600_resource(dst);
if (!cs || offset % 4 != 0 || size % 4 != 0 ||
dst->flags & PIPE_RESOURCE_FLAG_SPARSE) {
- ctx->clear_buffer(ctx, dst, offset, size, &clear_value, 4);
+ sctx->b.clear_buffer(&sctx->b, dst, offset, size, &clear_value, 4);
return;
}
/* the same maximum size as for copying */
ncopy = DIV_ROUND_UP(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE);
- si_need_dma_space(&sctx->b, ncopy * 4, rdst, NULL);
+ si_need_dma_space(sctx, ncopy * 4, rdst, NULL);
for (i = 0; i < ncopy; i++) {
csize = MIN2(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE);
unsigned pitch,
unsigned bpp)
{
- struct radeon_winsys_cs *cs = ctx->b.dma.cs;
+ struct radeon_winsys_cs *cs = ctx->dma_cs;
struct r600_texture *rsrc = (struct r600_texture*)src;
struct r600_texture *rdst = (struct r600_texture*)dst;
unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
struct r600_texture *rtiled = detile ? rsrc : rdst;
unsigned linear_lvl = detile ? dst_level : src_level;
unsigned tiled_lvl = detile ? src_level : dst_level;
- struct radeon_info *info = &ctx->screen->b.info;
+ struct radeon_info *info = &ctx->screen->info;
unsigned index = rtiled->surface.u.legacy.tiling_index[tiled_lvl];
unsigned tile_mode = info->si_tile_mode_array[index];
unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
height = rtiled->surface.u.legacy.level[tiled_lvl].nblk_y;
base = rtiled->surface.u.legacy.level[tiled_lvl].offset;
addr = rlinear->surface.u.legacy.level[linear_lvl].offset;
- addr += rlinear->surface.u.legacy.level[linear_lvl].slice_size * linear_z;
+ addr += (uint64_t)rlinear->surface.u.legacy.level[linear_lvl].slice_size_dw * 4 * linear_z;
addr += linear_y * pitch + linear_x * bpp;
bank_h = G_009910_BANK_HEIGHT(tile_mode);
bank_w = G_009910_BANK_WIDTH(tile_mode);
mt = G_009910_MICRO_TILE_MODE(tile_mode);
size = copy_height * pitch;
ncopy = DIV_ROUND_UP(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE);
- si_need_dma_space(&ctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
+ si_need_dma_space(ctx, ncopy * 9, &rdst->resource, &rsrc->resource);
for (i = 0; i < ncopy; i++) {
cheight = copy_height;
unsigned src_x, src_y;
unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
- if (sctx->b.dma.cs == NULL ||
+ if (sctx->dma_cs == NULL ||
src->flags & PIPE_RESOURCE_FLAG_SPARSE ||
dst->flags & PIPE_RESOURCE_FLAG_SPARSE) {
goto fallback;
goto fallback;
if (src_box->depth > 1 ||
- !si_prepare_for_dma_blit(&sctx->b, rdst, dst_level, dstx, dsty,
- dstz, rsrc, src_level, src_box))
+ !si_prepare_for_dma_blit(sctx, rdst, dst_level, dstx, dsty,
+ dstz, rsrc, src_level, src_box))
goto fallback;
src_x = util_format_get_nblocksx(src->format, src_box->x);
* dst_pitch == src_pitch
*/
src_offset= rsrc->surface.u.legacy.level[src_level].offset;
- src_offset += rsrc->surface.u.legacy.level[src_level].slice_size * src_box->z;
+ src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
src_offset += src_y * src_pitch + src_x * bpp;
dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
- dst_offset += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
+ dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
dst_offset += dst_y * dst_pitch + dst_x * bpp;
si_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset,
- rsrc->surface.u.legacy.level[src_level].slice_size);
+ (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4);
} else {
si_dma_copy_tile(sctx, dst, dst_level, dst_x, dst_y, dst_z,
src, src_level, src_x, src_y, src_box->z,
void si_init_dma_functions(struct si_context *sctx)
{
- sctx->b.dma_copy = si_dma_copy;
- sctx->b.dma_clear_buffer = si_dma_clear_buffer;
+ sctx->dma_copy = si_dma_copy;
+ sctx->dma_clear_buffer = si_dma_clear_buffer;
}
projects / mesa.git / blobdiff