gallium: add AMD-specific compute TGSI enums

[mesa.git] / src / gallium / drivers / radeonsi / si_fence.c

diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c
index b3212c1db351bcd6d734cea4d2f695ebcb876436..4df9e65dd08498b2252484507cfd18859f093738 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_fence.c
+++ b/src/gallium/drivers/radeonsi/si_fence.c
@@ -66,13 +66,12 @@ struct si_multi_fence {
  * \param old_value    Previous fence value (for a bug workaround)
  * \param new_value    Fence value to write for this event.
  */
-void si_cp_release_mem(struct si_context *ctx,
+void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
                       unsigned event, unsigned event_flags,
                       unsigned dst_sel, unsigned int_sel, unsigned data_sel,
                       struct si_resource *buf, uint64_t va,
                       uint32_t new_fence, unsigned query_type)
 {
-       struct radeon_cmdbuf *cs = ctx->gfx_cs;
        unsigned op = EVENT_TYPE(event) |
                      EVENT_INDEX(event == V_028A90_CS_DONE ||
                                  event == V_028A90_PS_DONE ? 6 : 5) |
@@ -80,8 +79,11 @@ void si_cp_release_mem(struct si_context *ctx,
        unsigned sel = EOP_DST_SEL(dst_sel) |
                       EOP_INT_SEL(int_sel) |
                       EOP_DATA_SEL(data_sel);
+       bool compute_ib = !ctx->has_graphics ||
+                         cs == ctx->prim_discard_compute_cs;
 
-       if (ctx->chip_class >= GFX9) {
+       if (ctx->chip_class >= GFX9 ||
+           (compute_ib && ctx->chip_class >= GFX7)) {
                /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
                 * counters) must immediately precede every timestamp event to
                 * prevent a GPU hang on GFX9.
@@ -89,7 +91,7 @@ void si_cp_release_mem(struct si_context *ctx,
                 * Occlusion queries don't need to do it here, because they
                 * always do ZPASS_DONE before the timestamp.
                 */
-               if (ctx->chip_class == GFX9 &&
+               if (ctx->chip_class == GFX9 && !compute_ib &&
                    query_type != PIPE_QUERY_OCCLUSION_COUNTER &&
                    query_type != PIPE_QUERY_OCCLUSION_PREDICATE &&
                    query_type != PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
@@ -106,14 +108,15 @@ void si_cp_release_mem(struct si_context *ctx,
                                                  RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
                }
 
-               radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0));
+               radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, ctx->chip_class >= GFX9 ? 6 : 5, 0));
                radeon_emit(cs, op);
                radeon_emit(cs, sel);
                radeon_emit(cs, va);            /* address lo */
                radeon_emit(cs, va >> 32);      /* address hi */
                radeon_emit(cs, new_fence);     /* immediate data lo */
                radeon_emit(cs, 0); /* immediate data hi */
-               radeon_emit(cs, 0); /* unused */
+               if (ctx->chip_class >= GFX9)
+                       radeon_emit(cs, 0); /* unused */
        } else {
                if (ctx->chip_class == GFX7 ||
                    ctx->chip_class == GFX8) {
@@ -178,8 +181,8 @@ static void si_add_fence_dependency(struct si_context *sctx,
        struct radeon_winsys *ws = sctx->ws;
 
        if (sctx->dma_cs)
-               ws->cs_add_fence_dependency(sctx->dma_cs, fence);
-       ws->cs_add_fence_dependency(sctx->gfx_cs, fence);
+               ws->cs_add_fence_dependency(sctx->dma_cs, fence, 0);
+       ws->cs_add_fence_dependency(sctx->gfx_cs, fence, 0);
 }
 
 static void si_add_syncobj_signal(struct si_context *sctx,
@@ -269,7 +272,7 @@ static void si_fine_fence_set(struct si_context *ctx,
 
                radeon_add_to_buffer_list(ctx, ctx->gfx_cs, fine->buf,
                                          RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
-               si_cp_release_mem(ctx,
+               si_cp_release_mem(ctx, ctx->gfx_cs,
                                  V_028A90_BOTTOM_OF_PIPE_TS, 0,
                                  EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
                                  EOP_DATA_SEL_VALUE_32BIT,
@@ -280,10 +283,10 @@ static void si_fine_fence_set(struct si_context *ctx,
        }
 }
 
-static boolean si_fence_finish(struct pipe_screen *screen,
-                              struct pipe_context *ctx,
-                              struct pipe_fence_handle *fence,
-                              uint64_t timeout)
+static bool si_fence_finish(struct pipe_screen *screen,
+                           struct pipe_context *ctx,
+                           struct pipe_fence_handle *fence,
+                           uint64_t timeout)
 {
        struct radeon_winsys *rws = ((struct si_screen*)screen)->ws;
        struct si_multi_fence *sfence = (struct si_multi_fence *)fence;