radeonsi: move PKT3_WRITE_DATA generation into a helper function

[mesa.git] / src / gallium / drivers / radeonsi / si_fence.c

diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c
index 3f22ee31ae813af28ddae166ee92efc4c0754f27..84bf4d10c2043c3f78b17d21152c80886a0ac720 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_fence.c
+++ b/src/gallium/drivers/radeonsi/si_fence.c
@@ -160,13 +160,11 @@ unsigned si_cp_write_fence_dwords(struct si_screen *screen)
        return dwords;
 }
 
-void si_cp_wait_mem(struct si_context *ctx,
+void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
                    uint64_t va, uint32_t ref, uint32_t mask, unsigned flags)
 {
-       struct radeon_cmdbuf *cs = ctx->gfx_cs;
-
        radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
-       radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1) | flags);
+       radeon_emit(cs, WAIT_REG_MEM_MEM_SPACE(1) | flags);
        radeon_emit(cs, va);
        radeon_emit(cs, va >> 32);
        radeon_emit(cs, ref); /* reference value */
@@ -261,24 +259,19 @@ static void si_fine_fence_set(struct si_context *ctx,
 
        *fence_ptr = 0;
 
-       uint64_t fence_va = fine->buf->gpu_address + fine->offset;
-
-       radeon_add_to_buffer_list(ctx, ctx->gfx_cs, fine->buf,
-                                 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
        if (flags & PIPE_FLUSH_TOP_OF_PIPE) {
-               struct radeon_cmdbuf *cs = ctx->gfx_cs;
-               radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
-               radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
-                       S_370_WR_CONFIRM(1) |
-                       S_370_ENGINE_SEL(V_370_PFP));
-               radeon_emit(cs, fence_va);
-               radeon_emit(cs, fence_va >> 32);
-               radeon_emit(cs, 0x80000000);
+               uint32_t value = 0x80000000;
+
+               si_cp_write_data(ctx, fine->buf, fine->offset, 4,
+                                V_370_MEM, V_370_PFP, &value);
        } else if (flags & PIPE_FLUSH_BOTTOM_OF_PIPE) {
+               uint64_t fence_va = fine->buf->gpu_address + fine->offset;
+
+               radeon_add_to_buffer_list(ctx, ctx->gfx_cs, fine->buf,
+                                         RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
                si_cp_release_mem(ctx,
                                  V_028A90_BOTTOM_OF_PIPE_TS, 0,
-                                 EOP_DST_SEL_MEM,
-                                 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
+                                 EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
                                  EOP_DATA_SEL_VALUE_32BIT,
                                  NULL, fence_va, 0x80000000,
                                  PIPE_QUERY_GPU_FINISHED);