{
struct radeon_winsys *ws = sctx->ws;
- if (sctx->dma_cs)
- ws->cs_add_fence_dependency(sctx->dma_cs, fence, 0);
+ if (sctx->sdma_cs)
+ ws->cs_add_fence_dependency(sctx->sdma_cs, fence, 0);
ws->cs_add_fence_dependency(sctx->gfx_cs, fence, 0);
}
}
}
-static boolean si_fence_finish(struct pipe_screen *screen,
- struct pipe_context *ctx,
- struct pipe_fence_handle *fence,
- uint64_t timeout)
+static bool si_fence_finish(struct pipe_screen *screen,
+ struct pipe_context *ctx,
+ struct pipe_fence_handle *fence,
+ uint64_t timeout)
{
struct radeon_winsys *rws = ((struct si_screen*)screen)->ws;
struct si_multi_fence *sfence = (struct si_multi_fence *)fence;
}
/* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
- if (sctx->dma_cs)
+ if (sctx->sdma_cs)
si_flush_dma_cs(sctx, rflags, fence ? &sdma_fence : NULL);
if (!radeon_emitted(sctx->gfx_cs, sctx->initial_gfx_cs_size)) {
assert(!fine.buf);
finish:
if (!(flags & (PIPE_FLUSH_DEFERRED | PIPE_FLUSH_ASYNC))) {
- if (sctx->dma_cs)
- ws->cs_sync_flush(sctx->dma_cs);
+ if (sctx->sdma_cs)
+ ws->cs_sync_flush(sctx->sdma_cs);
ws->cs_sync_flush(sctx->gfx_cs);
}
}