case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
- case PIPE_CAP_SM3:
+ case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
+ case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
+ case PIPE_CAP_VERTEX_SHADER_SATURATE:
case PIPE_CAP_SEAMLESS_CUBE_MAP:
case PIPE_CAP_PRIMITIVE_RESTART:
case PIPE_CAP_CONDITIONAL_RENDER:
case PIPE_CAP_QUERY_TIMESTAMP:
case PIPE_CAP_QUERY_TIME_ELAPSED:
case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
- case PIPE_CAP_QUERY_SO_OVERFLOW:
case PIPE_CAP_MEMOBJ:
case PIPE_CAP_LOAD_CONSTBUF:
case PIPE_CAP_INT64:
case PIPE_CAP_FBFETCH:
case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
case PIPE_CAP_IMAGE_LOAD_FORMATTED:
- case PIPE_CAP_PREFER_COMPUTE_BLIT_FOR_MULTIMEDIA:
- case PIPE_CAP_TGSI_DIV:
+ case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
+ case PIPE_CAP_TGSI_DIV:
return 1;
+ case PIPE_CAP_QUERY_SO_OVERFLOW:
+ return !sscreen->use_ngg_streamout;
+
+ case PIPE_CAP_POST_DEPTH_COVERAGE:
+ return sscreen->info.chip_class >= GFX10;
+
+ case PIPE_CAP_GRAPHICS:
+ return sscreen->info.has_graphics;
+
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
RADEON_SPARSE_PAGE_SIZE : 0;
case PIPE_CAP_PACKED_UNIFORMS:
+ case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
if (sscreen->options.enable_nir)
return 1;
return 0;
+ case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
+ if (sscreen->options.enable_nir)
+ return 0;
+ return 1;
+
/* Unsupported features. */
case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
case PIPE_CAP_UMA:
case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
- case PIPE_CAP_POST_DEPTH_COVERAGE:
case PIPE_CAP_TILE_RASTER_ORDER:
case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
case PIPE_CAP_CONTEXT_PRIORITY_MASK:
return sscreen->info.pci_dev;
case PIPE_CAP_PCI_FUNCTION:
return sscreen->info.pci_func;
+ case PIPE_CAP_TGSI_ATOMINC_WRAP:
+ return HAVE_LLVM >= 0x1000;
default:
return u_pipe_screen_get_param_defaults(pscreen, param);
.lower_sub = true,
.lower_ffma = true,
.lower_fmod = true,
- .lower_pack_snorm_2x16 = true,
.lower_pack_snorm_4x8 = true,
- .lower_pack_unorm_2x16 = true,
.lower_pack_unorm_4x8 = true,
.lower_unpack_snorm_2x16 = true,
.lower_unpack_snorm_4x8 = true,
.lower_rotate = true,
.optimize_sample_mask_in = true,
.max_unroll_iterations = 32,
+ .use_interpolated_input_intrinsics = true,
};
static const void *
return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
return false;
case PIPE_VIDEO_FORMAT_JPEG:
- if (sscreen->info.family == CHIP_RAVEN ||
- sscreen->info.family == CHIP_RAVEN2 ||
- sscreen->info.family == CHIP_NAVI10)
+ if (sscreen->info.family >= CHIP_RAVEN)
return true;
if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
return false;
}
}
-static boolean si_vid_is_format_supported(struct pipe_screen *screen,
- enum pipe_format format,
- enum pipe_video_profile profile,
- enum pipe_video_entrypoint entrypoint)
+static bool si_vid_is_format_supported(struct pipe_screen *screen,
+ enum pipe_format format,
+ enum pipe_video_profile profile,
+ enum pipe_video_entrypoint entrypoint)
{
/* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
return (format == PIPE_FORMAT_NV12) ||
(format == PIPE_FORMAT_P016);
+ /* Vp9 profile 2 supports 10 bit decoding using P016 */
+ if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
+ return format == PIPE_FORMAT_P016;
+
+
/* we can only handle this one with UVD */
if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
return format == PIPE_FORMAT_NV12;
case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
if (ret) {
uint32_t *subgroup_size = ret;
- *subgroup_size = 64;
+ *subgroup_size = sscreen->compute_wave_size;
}
return sizeof(uint32_t);
case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK: