/*
* Copyright 2017 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
#include "si_pipe.h"
#include "radeon/radeon_video.h"
#include "radeon/radeon_vce.h"
+#include "radeon/radeon_uvd_enc.h"
#include "ac_llvm_util.h"
#include "vl/vl_decoder.h"
#include "vl/vl_video_buffer.h"
const char *si_get_family_name(const struct si_screen *sscreen)
{
- switch (sscreen->b.info.family) {
+ switch (sscreen->info.family) {
case CHIP_TAHITI: return "AMD TAHITI";
case CHIP_PITCAIRN: return "AMD PITCAIRN";
case CHIP_VERDE: return "AMD CAPE VERDE";
case CHIP_ICELAND: return "AMD ICELAND";
case CHIP_CARRIZO: return "AMD CARRIZO";
case CHIP_FIJI: return "AMD FIJI";
+ case CHIP_STONEY: return "AMD STONEY";
case CHIP_POLARIS10: return "AMD POLARIS10";
case CHIP_POLARIS11: return "AMD POLARIS11";
case CHIP_POLARIS12: return "AMD POLARIS12";
- case CHIP_STONEY: return "AMD STONEY";
+ case CHIP_VEGAM: return "AMD VEGAM";
case CHIP_VEGA10: return "AMD VEGA10";
+ case CHIP_VEGA12: return "AMD VEGA12";
case CHIP_RAVEN: return "AMD RAVEN";
default: return "AMD unknown";
}
}
-static bool si_have_tgsi_compute(struct si_screen *sscreen)
-{
- /* Old kernels disallowed some register writes for SI
- * that are used for indirect dispatches. */
- return (sscreen->b.chip_class >= CIK ||
- sscreen->b.info.drm_major == 3 ||
- (sscreen->b.info.drm_major == 2 &&
- sscreen->b.info.drm_minor >= 45));
-}
-
static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
{
struct si_screen *sscreen = (struct si_screen *)pscreen;
switch (param) {
/* Supported features (boolean caps). */
case PIPE_CAP_ACCELERATED:
- case PIPE_CAP_TWO_SIDED_STENCIL:
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
case PIPE_CAP_ANISOTROPIC_FILTER:
case PIPE_CAP_POINT_SPRITE:
case PIPE_CAP_OCCLUSION_QUERY:
- case PIPE_CAP_TEXTURE_SHADOW_MAP:
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_TEXTURE_SWIZZLE:
case PIPE_CAP_INDEP_BLEND_FUNC:
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
- case PIPE_CAP_USER_CONSTANT_BUFFERS:
case PIPE_CAP_START_INSTANCE:
case PIPE_CAP_NPOT_TEXTURES:
case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
case PIPE_CAP_INVALIDATE_BUFFER:
case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
+ case PIPE_CAP_QUERY_BUFFER_OBJECT:
case PIPE_CAP_QUERY_MEMORY_INFO:
case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
- return 1;
-
- case PIPE_CAP_TGSI_VOTE:
- return HAVE_LLVM >= 0x0400;
-
case PIPE_CAP_TGSI_BALLOT:
- return HAVE_LLVM >= 0x0500;
+ case PIPE_CAP_TGSI_VOTE:
+ case PIPE_CAP_TGSI_FS_FBFETCH:
+ return 1;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
- return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
+ return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
- return (sscreen->b.info.drm_major == 2 &&
- sscreen->b.info.drm_minor >= 43) ||
- sscreen->b.info.drm_major == 3;
+ return sscreen->info.has_gpu_reset_status_query ||
+ sscreen->info.has_gpu_reset_counter_query;
case PIPE_CAP_TEXTURE_MULTISAMPLE:
- /* 2D tiling on CIK is supported since DRM 2.35.0 */
- return sscreen->b.chip_class < CIK ||
- (sscreen->b.info.drm_major == 2 &&
- sscreen->b.info.drm_minor >= 35) ||
- sscreen->b.info.drm_major == 3;
+ return sscreen->info.has_2d_tiling;
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
- return R600_MAP_BUFFER_ALIGNMENT;
+ return SI_MAP_BUFFER_ALIGNMENT;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
return 4;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
- if (sscreen->b.debug_flags & DBG(NIR))
- return 140; /* no geometry and tessellation shaders yet */
- if (si_have_tgsi_compute(sscreen))
+ if (sscreen->info.has_indirect_compute_dispatch)
return 450;
return 420;
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
- return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
+ return MIN2(sscreen->info.max_alloc_size, INT_MAX);
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
- /* SI doesn't support unaligned loads.
- * CIK needs DRM 2.50.0 on radeon. */
- return sscreen->b.chip_class == SI ||
- (sscreen->b.info.drm_major == 2 &&
- sscreen->b.info.drm_minor < 50);
+ return !sscreen->info.has_unaligned_shader_loads;
case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
- /* TODO: GFX9 hangs. */
- if (sscreen->b.chip_class >= GFX9)
- return 0;
- /* Disable on SI due to VM faults in CP DMA. Enable once these
- * faults are mitigated in software.
- */
- if (sscreen->b.chip_class >= CIK &&
- sscreen->b.info.drm_major == 3 &&
- sscreen->b.info.drm_minor >= 13)
- return RADEON_SPARSE_PAGE_SIZE;
+ return sscreen->info.has_sparse_vm_mappings ?
+ RADEON_SPARSE_PAGE_SIZE : 0;
+
+ case PIPE_CAP_PACKED_UNIFORMS:
+ if (sscreen->debug_flags & DBG(NIR))
+ return 1;
return 0;
/* Unsupported features. */
case PIPE_CAP_VERTEXID_NOBASE:
case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
case PIPE_CAP_MAX_WINDOW_RECTANGLES:
- case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
case PIPE_CAP_UMA:
case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
case PIPE_CAP_POST_DEPTH_COVERAGE:
case PIPE_CAP_TILE_RASTER_ORDER:
case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+ case PIPE_CAP_CONTEXT_PRIORITY_MASK:
+ case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
+ case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
+ case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
+ case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
+ case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
+ case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
return 0;
- case PIPE_CAP_NATIVE_FENCE_FD:
- return sscreen->b.info.has_sync_file;
+ case PIPE_CAP_FENCE_SIGNAL:
+ return sscreen->info.has_syncobj;
- case PIPE_CAP_QUERY_BUFFER_OBJECT:
- return si_have_tgsi_compute(sscreen);
+ case PIPE_CAP_CONSTBUF0_FLAGS:
+ return SI_RESOURCE_FLAG_32BIT;
+
+ case PIPE_CAP_NATIVE_FENCE_FD:
+ return sscreen->info.has_fence_to_handle;
case PIPE_CAP_DRAW_PARAMETERS:
case PIPE_CAP_MULTI_DRAW_INDIRECT:
return 30;
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
- return sscreen->b.chip_class <= VI ?
+ return sscreen->info.chip_class <= VI ?
PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
/* Stream output. */
case PIPE_CAP_VENDOR_ID:
return ATI_VENDOR_ID;
case PIPE_CAP_DEVICE_ID:
- return sscreen->b.info.pci_id;
+ return sscreen->info.pci_id;
case PIPE_CAP_VIDEO_MEMORY:
- return sscreen->b.info.vram_size >> 20;
+ return sscreen->info.vram_size >> 20;
case PIPE_CAP_PCI_GROUP:
- return sscreen->b.info.pci_domain;
+ return sscreen->info.pci_domain;
case PIPE_CAP_PCI_BUS:
- return sscreen->b.info.pci_bus;
+ return sscreen->info.pci_bus;
case PIPE_CAP_PCI_DEVICE:
- return sscreen->b.info.pci_dev;
+ return sscreen->info.pci_dev;
case PIPE_CAP_PCI_FUNCTION:
- return sscreen->b.info.pci_func;
+ return sscreen->info.pci_func;
}
return 0;
}
return 16.0f;
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
return 16.0f;
- case PIPE_CAPF_GUARD_BAND_LEFT:
- case PIPE_CAPF_GUARD_BAND_TOP:
- case PIPE_CAPF_GUARD_BAND_RIGHT:
- case PIPE_CAPF_GUARD_BAND_BOTTOM:
+ case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
+ case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
+ case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
return 0.0f;
}
return 0.0f;
break;
case PIPE_SHADER_COMPUTE:
switch (param) {
- case PIPE_SHADER_CAP_PREFERRED_IR:
- return PIPE_SHADER_IR_NATIVE;
-
case PIPE_SHADER_CAP_SUPPORTED_IRS: {
int ir = 1 << PIPE_SHADER_IR_NATIVE;
- if (si_have_tgsi_compute(sscreen))
+ if (sscreen->info.has_indirect_compute_dispatch)
ir |= 1 << PIPE_SHADER_IR_TGSI;
return ir;
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
return SI_NUM_IMAGES;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
+ if (sscreen->debug_flags & DBG(NIR))
+ return 0;
return 32;
case PIPE_SHADER_CAP_PREFERRED_IR:
- if (sscreen->b.debug_flags & DBG(NIR) &&
- (shader == PIPE_SHADER_VERTEX ||
- shader == PIPE_SHADER_FRAGMENT))
+ if (sscreen->debug_flags & DBG(NIR))
return PIPE_SHADER_IR_NIR;
return PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
/* TODO: Indirect indexing of GS inputs is unimplemented. */
- return shader != PIPE_SHADER_GEOMETRY &&
- (sscreen->llvm_has_working_vgpr_indexing ||
- /* TCS and TES load inputs directly from LDS or
- * offchip memory, so indirect indexing is trivial. */
- shader == PIPE_SHADER_TESS_CTRL ||
- shader == PIPE_SHADER_TESS_EVAL);
+ if (shader == PIPE_SHADER_GEOMETRY)
+ return 0;
+
+ if (shader == PIPE_SHADER_VERTEX &&
+ !sscreen->llvm_has_working_vgpr_indexing)
+ return 0;
+
+ /* Doing indirect indexing on GFX9 with LLVM 6.0 hangs.
+ * This means we don't support INTERP instructions with
+ * indirect indexing on inputs.
+ */
+ if (shader == PIPE_SHADER_FRAGMENT &&
+ !sscreen->llvm_has_working_vgpr_indexing &&
+ HAVE_LLVM < 0x0700)
+ return 0;
+
+ /* TCS and TES load inputs directly from LDS or offchip
+ * memory, so indirect indexing is always supported.
+ * PS has to support indirect indexing, because we can't
+ * lower that to TEMPs for INTERP instructions.
+ */
+ return 1;
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return sscreen->llvm_has_working_vgpr_indexing ||
}
static const struct nir_shader_compiler_options nir_options = {
- .vertex_id_zero_based = true,
.lower_scmp = true,
.lower_flrp32 = true,
+ .lower_flrp64 = true,
+ .lower_fpow = true,
.lower_fsat = true,
.lower_fdiv = true,
.lower_sub = true,
{
struct si_screen *sscreen = (struct si_screen *)pscreen;
- ac_compute_device_uuid(&sscreen->b.info, uuid, PIPE_UUID_SIZE);
+ ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
}
static const char* si_get_name(struct pipe_screen *pscreen)
{
struct si_screen *sscreen = (struct si_screen*)pscreen;
- return sscreen->b.renderer_string;
+ return sscreen->renderer_string;
}
static int si_get_video_param_no_decode(struct pipe_screen *screen,
if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
switch (param) {
case PIPE_VIDEO_CAP_SUPPORTED:
- return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
- (si_vce_is_fw_version_supported(&sscreen->b) ||
- sscreen->b.family == CHIP_RAVEN);
+ return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
+ (si_vce_is_fw_version_supported(sscreen) ||
+ sscreen->info.family == CHIP_RAVEN)) ||
+ (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
+ (sscreen->info.family == CHIP_RAVEN ||
+ si_radeon_uvd_enc_supported(sscreen)));
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
return 1;
case PIPE_VIDEO_CAP_MAX_WIDTH:
- return (sscreen->b.family < CHIP_TONGA) ? 2048 : 4096;
+ return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
case PIPE_VIDEO_CAP_MAX_HEIGHT:
- return (sscreen->b.family < CHIP_TONGA) ? 1152 : 2304;
+ return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
case PIPE_VIDEO_CAP_PREFERED_FORMAT:
return PIPE_FORMAT_NV12;
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
return true;
case PIPE_VIDEO_CAP_STACKED_FRAMES:
- return (sscreen->b.family < CHIP_TONGA) ? 1 : 2;
+ return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
default:
return 0;
}
case PIPE_VIDEO_FORMAT_MPEG4:
return 1;
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
- if ((sscreen->b.family == CHIP_POLARIS10 ||
- sscreen->b.family == CHIP_POLARIS11) &&
- sscreen->b.info.uvd_fw_version < UVD_FW_1_66_16 ) {
+ if ((sscreen->info.family == CHIP_POLARIS10 ||
+ sscreen->info.family == CHIP_POLARIS11) &&
+ sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
return false;
}
return true;
case PIPE_VIDEO_FORMAT_HEVC:
/* Carrizo only supports HEVC Main */
- if (sscreen->b.family >= CHIP_STONEY)
+ if (sscreen->info.family >= CHIP_STONEY)
return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
- else if (sscreen->b.family >= CHIP_CARRIZO)
+ else if (sscreen->info.family >= CHIP_CARRIZO)
return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
return false;
case PIPE_VIDEO_FORMAT_JPEG:
- if (sscreen->b.family < CHIP_CARRIZO || sscreen->b.family >= CHIP_VEGA10)
+ if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
return false;
- if (!(sscreen->b.info.drm_major == 3 && sscreen->b.info.drm_minor >= 19)) {
+ if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
RVID_ERR("No MJPEG support for the kernel version\n");
return false;
}
return true;
+ case PIPE_VIDEO_FORMAT_VP9:
+ if (sscreen->info.family < CHIP_RAVEN)
+ return false;
+ return true;
default:
return false;
}
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
return 1;
case PIPE_VIDEO_CAP_MAX_WIDTH:
- return (sscreen->b.family < CHIP_TONGA) ? 2048 : 4096;
+ return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
case PIPE_VIDEO_CAP_MAX_HEIGHT:
- return (sscreen->b.family < CHIP_TONGA) ? 1152 : 4096;
+ return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
case PIPE_VIDEO_CAP_PREFERED_FORMAT:
- if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
+ if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
+ profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
return PIPE_FORMAT_P016;
else
return PIPE_FORMAT_NV12;
return false; //The firmware doesn't support interlaced HEVC.
else if (format == PIPE_VIDEO_FORMAT_JPEG)
return false;
+ else if (format == PIPE_VIDEO_FORMAT_VP9)
+ return false;
return true;
}
case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
- return (sscreen->b.family < CHIP_TONGA) ? 41 : 52;
+ return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
case PIPE_VIDEO_PROFILE_HEVC_MAIN:
case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
return 186;
static unsigned get_max_threads_per_block(struct si_screen *screen,
enum pipe_shader_ir ir_type)
{
- if (ir_type != PIPE_SHADER_IR_TGSI)
+ if (ir_type == PIPE_SHADER_IR_NATIVE)
return 256;
/* Only 16 waves per thread-group on gfx9. */
- if (screen->b.chip_class >= GFX9)
+ if (screen->info.chip_class >= GFX9)
return 1024;
/* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
//TODO: select these params by asic
switch (param) {
case PIPE_COMPUTE_CAP_IR_TARGET: {
- const char *gpu;
- const char *triple;
-
- if (HAVE_LLVM < 0x0400)
- triple = "amdgcn--";
- else
- triple = "amdgcn-mesa-mesa3d";
+ const char *gpu, *triple;
- gpu = ac_get_llvm_processor_name(sscreen->b.family);
+ triple = "amdgcn-mesa-mesa3d";
+ gpu = ac_get_llvm_processor_name(sscreen->info.family);
if (ret) {
sprintf(ret, "%s-%s", gpu, triple);
}
* 4 * MAX_MEM_ALLOC_SIZE.
*/
*max_global_size = MIN2(4 * max_mem_alloc_size,
- MAX2(sscreen->b.info.gart_size,
- sscreen->b.info.vram_size));
+ MAX2(sscreen->info.gart_size,
+ sscreen->info.vram_size));
}
return sizeof(uint64_t);
if (ret) {
uint64_t *max_mem_alloc_size = ret;
- *max_mem_alloc_size = sscreen->b.info.max_alloc_size;
+ *max_mem_alloc_size = sscreen->info.max_alloc_size;
}
return sizeof(uint64_t);
case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
if (ret) {
uint32_t *max_clock_frequency = ret;
- *max_clock_frequency = sscreen->b.info.max_shader_clock;
+ *max_clock_frequency = sscreen->info.max_shader_clock;
}
return sizeof(uint32_t);
case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
if (ret) {
uint32_t *max_compute_units = ret;
- *max_compute_units = sscreen->b.info.num_good_compute_units;
+ *max_compute_units = sscreen->info.num_good_compute_units;
}
return sizeof(uint32_t);
case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
if (ret) {
uint64_t *max_variable_threads_per_block = ret;
- if (ir_type == PIPE_SHADER_IR_TGSI)
- *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
- else
+ if (ir_type == PIPE_SHADER_IR_NATIVE)
*max_variable_threads_per_block = 0;
+ else
+ *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
}
return sizeof(uint64_t);
}
{
struct si_screen *sscreen = (struct si_screen*)screen;
- return 1000000 * sscreen->b.ws->query_value(sscreen->b.ws, RADEON_TIMESTAMP) /
- sscreen->b.info.clock_crystal_freq;
+ return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
+ sscreen->info.clock_crystal_freq;
}
static void si_query_memory_info(struct pipe_screen *screen,
struct pipe_memory_info *info)
{
struct si_screen *sscreen = (struct si_screen*)screen;
- struct radeon_winsys *ws = sscreen->b.ws;
+ struct radeon_winsys *ws = sscreen->ws;
unsigned vram_usage, gtt_usage;
- info->total_device_memory = sscreen->b.info.vram_size / 1024;
- info->total_staging_memory = sscreen->b.info.gart_size / 1024;
+ info->total_device_memory = sscreen->info.vram_size / 1024;
+ info->total_staging_memory = sscreen->info.gart_size / 1024;
/* The real TTM memory usage is somewhat random, because:
*
info->device_memory_evicted =
ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
- if (sscreen->b.info.drm_major == 3 && sscreen->b.info.drm_minor >= 4)
+ if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
info->nr_device_memory_evictions =
ws->query_value(ws, RADEON_NUM_EVICTIONS);
else
{
struct si_screen *sscreen = (struct si_screen*)pscreen;
- return sscreen->b.disk_shader_cache;
+ return sscreen->disk_shader_cache;
}
static void si_init_renderer_string(struct si_screen *sscreen)
{
- struct radeon_winsys *ws = sscreen->b.ws;
- char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
+ struct radeon_winsys *ws = sscreen->ws;
+ char family_name[32] = {}, kernel_version[128] = {};
struct utsname uname_data;
const char *chip_name = si_get_marketing_name(ws);
if (chip_name)
- snprintf(family_name, sizeof(family_name), "%s / ",
+ snprintf(family_name, sizeof(family_name), "%s, ",
si_get_family_name(sscreen) + 4);
else
chip_name = si_get_family_name(sscreen);
if (uname(&uname_data) == 0)
snprintf(kernel_version, sizeof(kernel_version),
- " / %s", uname_data.release);
-
- if (HAVE_LLVM > 0) {
- snprintf(llvm_string, sizeof(llvm_string),
- ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
- HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
- }
-
- snprintf(sscreen->b.renderer_string, sizeof(sscreen->b.renderer_string),
- "%s (%sDRM %i.%i.%i%s%s)",
- chip_name, family_name, sscreen->b.info.drm_major,
- sscreen->b.info.drm_minor, sscreen->b.info.drm_patchlevel,
- kernel_version, llvm_string);
+ ", %s", uname_data.release);
+
+ snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
+ "%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)",
+ chip_name, family_name, sscreen->info.drm_major,
+ sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
+ kernel_version,
+ (HAVE_LLVM >> 8) & 0xff,
+ HAVE_LLVM & 0xff,
+ MESA_LLVM_VERSION_PATCH);
}
void si_init_screen_get_functions(struct si_screen *sscreen)
{
- sscreen->b.b.get_name = si_get_name;
- sscreen->b.b.get_vendor = si_get_vendor;
- sscreen->b.b.get_device_vendor = si_get_device_vendor;
- sscreen->b.b.get_param = si_get_param;
- sscreen->b.b.get_paramf = si_get_paramf;
- sscreen->b.b.get_compute_param = si_get_compute_param;
- sscreen->b.b.get_timestamp = si_get_timestamp;
- sscreen->b.b.get_shader_param = si_get_shader_param;
- sscreen->b.b.get_compiler_options = si_get_compiler_options;
- sscreen->b.b.get_device_uuid = si_get_device_uuid;
- sscreen->b.b.get_driver_uuid = si_get_driver_uuid;
- sscreen->b.b.query_memory_info = si_query_memory_info;
- sscreen->b.b.get_disk_shader_cache = si_get_disk_shader_cache;
-
- if (sscreen->b.info.has_hw_decode) {
- sscreen->b.b.get_video_param = si_get_video_param;
- sscreen->b.b.is_video_format_supported = si_vid_is_format_supported;
+ sscreen->b.get_name = si_get_name;
+ sscreen->b.get_vendor = si_get_vendor;
+ sscreen->b.get_device_vendor = si_get_device_vendor;
+ sscreen->b.get_param = si_get_param;
+ sscreen->b.get_paramf = si_get_paramf;
+ sscreen->b.get_compute_param = si_get_compute_param;
+ sscreen->b.get_timestamp = si_get_timestamp;
+ sscreen->b.get_shader_param = si_get_shader_param;
+ sscreen->b.get_compiler_options = si_get_compiler_options;
+ sscreen->b.get_device_uuid = si_get_device_uuid;
+ sscreen->b.get_driver_uuid = si_get_driver_uuid;
+ sscreen->b.query_memory_info = si_query_memory_info;
+ sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
+
+ if (sscreen->info.has_hw_decode) {
+ sscreen->b.get_video_param = si_get_video_param;
+ sscreen->b.is_video_format_supported = si_vid_is_format_supported;
} else {
- sscreen->b.b.get_video_param = si_get_video_param_no_decode;
- sscreen->b.b.is_video_format_supported = vl_video_buffer_is_format_supported;
+ sscreen->b.get_video_param = si_get_video_param_no_decode;
+ sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
}
si_init_renderer_string(sscreen);
projects / mesa.git / blobdiff