case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
+ case PIPE_CAP_TGSI_BALLOT:
case PIPE_CAP_TGSI_VOTE:
case PIPE_CAP_TGSI_FS_FBFETCH:
return 1;
- case PIPE_CAP_TGSI_BALLOT:
- return HAVE_LLVM >= 0x0500;
-
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
sscreen->info.has_gpu_reset_counter_query;
case PIPE_CAP_TEXTURE_MULTISAMPLE:
- /* 2D tiling on CIK is supported since DRM 2.35.0 */
- return sscreen->info.chip_class < CIK ||
- (sscreen->info.drm_major == 2 &&
- sscreen->info.drm_minor >= 35) ||
- sscreen->info.drm_major == 3;
+ return sscreen->info.has_2d_tiling;
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
return SI_MAP_BUFFER_ALIGNMENT;
return !sscreen->info.has_unaligned_shader_loads;
case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
- /* TODO: GFX9 hangs. */
- if (sscreen->info.chip_class >= GFX9)
- return 0;
- /* Disable on SI due to VM faults in CP DMA. Enable once these
- * faults are mitigated in software.
- */
- if (sscreen->info.chip_class >= CIK &&
- sscreen->info.drm_major == 3 &&
- sscreen->info.drm_minor >= 13)
- return RADEON_SPARSE_PAGE_SIZE;
- return 0;
+ return sscreen->info.has_sparse_vm_mappings ?
+ RADEON_SPARSE_PAGE_SIZE : 0;
case PIPE_CAP_PACKED_UNIFORMS:
if (sscreen->debug_flags & DBG(NIR))