nv50: disable compute

[mesa.git] / src / gallium / drivers / radeonsi / si_get.c

diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index d373c1a967dc2bea37145eead43d392a966cd28a..a5cb209b59ee00194563ceee206a59c9b64056d3 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -71,6 +71,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_BLEND_EQUATION_SEPARATE:
        case PIPE_CAP_TEXTURE_SWIZZLE:
        case PIPE_CAP_DEPTH_CLIP_DISABLE:
+       case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
        case PIPE_CAP_SHADER_STENCIL_EXPORT:
        case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
        case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
@@ -189,6 +190,10 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
                                return 450;
                return 420;
 
+       case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
+               /* Optimal number for good TexSubImage performance on Polaris10. */
+               return 64 * 1024 * 1024;
+
        case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
        case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
                return MIN2(sscreen->info.max_alloc_size, INT_MAX);
@@ -249,6 +254,9 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
                return 30;
 
+       case PIPE_CAP_MAX_VARYINGS:
+               return 32;
+
        case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
                return sscreen->info.chip_class <= VI ?
                        PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
@@ -286,6 +294,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_MAX_VIEWPORTS:
                return SI_MAX_VIEWPORTS;
        case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
+       case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
        case PIPE_CAP_MAX_RENDER_TARGETS:
                return 8;
        case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
@@ -327,9 +336,12 @@ static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
        switch (param) {
        case PIPE_CAPF_MAX_LINE_WIDTH:
        case PIPE_CAPF_MAX_LINE_WIDTH_AA:
+               /* This depends on the quant mode, though the precise interactions
+                * are unknown. */
+               return 2048;
        case PIPE_CAPF_MAX_POINT_WIDTH:
        case PIPE_CAPF_MAX_POINT_WIDTH_AA:
-               return 8192.0f;
+               return SI_MAX_POINT_SIZE;
        case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
                return 16.0f;
        case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
@@ -446,15 +458,6 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
                    !sscreen->llvm_has_working_vgpr_indexing)
                        return 0;
 
-               /* Doing indirect indexing on GFX9 with LLVM 6.0 hangs.
-                * This means we don't support INTERP instructions with
-                * indirect indexing on inputs.
-                */
-               if (shader == PIPE_SHADER_FRAGMENT &&
-                   !sscreen->llvm_has_working_vgpr_indexing &&
-                   HAVE_LLVM < 0x0700)
-                       return 0;
-
                /* TCS and TES load inputs directly from LDS or offchip
                 * memory, so indirect indexing is always supported.
                 * PS has to support indirect indexing, because we can't
@@ -483,7 +486,6 @@ static const struct nir_shader_compiler_options nir_options = {
        .lower_scmp = true,
        .lower_flrp32 = true,
        .lower_flrp64 = true,
-       .lower_fpow = true,
        .lower_fsat = true,
        .lower_fdiv = true,
        .lower_sub = true,
@@ -571,10 +573,12 @@ static int si_get_video_param(struct pipe_screen *screen,
                case PIPE_VIDEO_CAP_SUPPORTED:
                        return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
                                (si_vce_is_fw_version_supported(sscreen) ||
-                               sscreen->info.family == CHIP_RAVEN)) ||
+                                sscreen->info.family == CHIP_RAVEN ||
+                                sscreen->info.family == CHIP_RAVEN2)) ||
                                (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
                                (sscreen->info.family == CHIP_RAVEN ||
-                               si_radeon_uvd_enc_supported(sscreen)));
+                                sscreen->info.family == CHIP_RAVEN2 ||
+                                si_radeon_uvd_enc_supported(sscreen)));
                case PIPE_VIDEO_CAP_NPOT_TEXTURES:
                        return 1;
                case PIPE_VIDEO_CAP_MAX_WIDTH:
@@ -622,6 +626,9 @@ static int si_get_video_param(struct pipe_screen *screen,
                                return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
                        return false;
                case PIPE_VIDEO_FORMAT_JPEG:
+                       if (sscreen->info.family == CHIP_RAVEN ||
+                           sscreen->info.family == CHIP_RAVEN2)
+                               return true;
                        if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
                                return false;
                        if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {