radeonsi/gfx10: move s_sendmsg gs_alloc_req to the beginning of shaders

[mesa.git] / src / gallium / drivers / radeonsi / si_gfx_cs.c

diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 277a25a0b3ee47304d528333544c67556f0887b6..270304ae9cbeaba36bb1ffebb81c6f383474b730 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -97,7 +97,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
            (!wait_flags || !ctx->gfx_last_ib_is_busy))
                return;
 
-       if (si_check_device_reset(ctx))
+       if (ctx->b.get_device_reset_status(&ctx->b) != PIPE_NO_RESET)
                return;
 
        if (ctx->screen->debug_flags & DBG(CHECK_VM))
@@ -110,7 +110,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
         * If the driver flushes the GFX IB internally, and it should never ask
         * for a fence handle.
         */
-       assert(!radeon_emitted(ctx->dma_cs, 0) || fence == NULL);
+       assert(!radeon_emitted(ctx->sdma_cs, 0) || fence == NULL);
 
        /* Update the sdma_uploads list by flushing the uploader. */
        u_upload_unmap(ctx->b.const_uploader);
@@ -119,20 +119,18 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
        ctx->sdma_uploads_in_progress = true;
        for (unsigned i = 0; i < ctx->num_sdma_uploads; i++) {
                struct si_sdma_upload *up = &ctx->sdma_uploads[i];
-               struct pipe_box box;
 
                assert(up->src_offset % 4 == 0 && up->dst_offset % 4 == 0 &&
                       up->size % 4 == 0);
 
-               u_box_1d(up->src_offset, up->size, &box);
-               ctx->dma_copy(&ctx->b, &up->dst->b.b, 0, up->dst_offset, 0, 0,
-                             &up->src->b.b, 0, &box);
+               si_sdma_copy_buffer(ctx, &up->dst->b.b, &up->src->b.b,
+                                   up->dst_offset, up->src_offset, up->size);
        }
        ctx->sdma_uploads_in_progress = false;
        si_unref_sdma_uploads(ctx);
 
        /* Flush SDMA (preamble IB). */
-       if (radeon_emitted(ctx->dma_cs, 0))
+       if (radeon_emitted(ctx->sdma_cs, 0))
                si_flush_dma_cs(ctx, flags, NULL);
 
        if (radeon_emitted(ctx->prim_discard_compute_cs, 0)) {
@@ -154,7 +152,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
        }
 
        if (ctx->has_graphics) {
-               if (!LIST_IS_EMPTY(&ctx->active_queries))
+               if (!list_is_empty(&ctx->active_queries))
                        si_suspend_queries(ctx);
 
                ctx->streamout.suspended = false;
@@ -162,11 +160,11 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
                        si_emit_streamout_end(ctx);
                        ctx->streamout.suspended = true;
 
-                       /* Since streamout uses GDS on gfx10, we need to make
-                        * GDS idle when we leave the IB, otherwise another
-                        * process might overwrite it while our shaders are busy.
+                       /* Since NGG streamout uses GDS, we need to make GDS
+                        * idle when we leave the IB, otherwise another process
+                        * might overwrite it while our shaders are busy.
                         */
-                       if (ctx->chip_class >= GFX10)
+                       if (ctx->screen->use_ngg_streamout)
                                wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
                }
        }
@@ -303,7 +301,7 @@ void si_allocate_gds(struct si_context *sctx)
        if (sctx->gds)
                return;
 
-       assert(sctx->chip_class >= GFX10); /* for gfx10 streamout */
+       assert(sctx->screen->use_ngg_streamout);
 
        /* 4 streamout GDS counters.
         * We need 256B (64 dw) of GDS, otherwise streamout hangs.
@@ -372,7 +370,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
                ctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
 
        /* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
-       bool has_clear_state = ctx->screen->has_clear_state;
+       bool has_clear_state = ctx->screen->info.has_clear_state;
        if (has_clear_state) {
                ctx->framebuffer.dirty_cbufs =
                         u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs);
@@ -405,7 +403,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
                si_mark_atom_dirty(ctx, &ctx->atoms.s.dpbb_state);
        si_mark_atom_dirty(ctx, &ctx->atoms.s.stencil_ref);
        si_mark_atom_dirty(ctx, &ctx->atoms.s.spi_map);
-       if (ctx->chip_class < GFX10)
+       if (!ctx->screen->use_ngg_streamout)
                si_mark_atom_dirty(ctx, &ctx->atoms.s.streamout_enable);
        si_mark_atom_dirty(ctx, &ctx->atoms.s.render_cond);
        /* CLEAR_STATE disables all window rectangles. */
@@ -426,7 +424,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
                si_streamout_buffers_dirty(ctx);
        }
 
-       if (!LIST_IS_EMPTY(&ctx->active_queries))
+       if (!list_is_empty(&ctx->active_queries))
                si_resume_queries(ctx);
 
        assert(!ctx->gfx_cs->prev_dw);
@@ -440,15 +438,13 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
        ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
        ctx->last_prim = -1;
        ctx->last_multi_vgt_param = -1;
-       ctx->last_rast_prim = -1;
-       ctx->last_flatshade_first = -1;
-       ctx->last_sc_line_stipple = ~0;
        ctx->last_vs_state = ~0;
        ctx->last_ls = NULL;
        ctx->last_tcs = NULL;
        ctx->last_tes_sh_base = -1;
        ctx->last_num_tcs_input_cp = -1;
        ctx->last_ls_hs_config = -1; /* impossible value */
+       ctx->last_binning_enabled = -1;
 
        ctx->prim_discard_compute_ib_initialized = false;
 
@@ -463,6 +459,8 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
 
         ctx->index_ring_offset = 0;
 
+       STATIC_ASSERT(SI_NUM_TRACKED_REGS <= sizeof(ctx->tracked_regs.reg_saved) * 8);
+
        if (has_clear_state) {
                ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_CONTROL] = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_DB_COUNT_CONTROL] = 0x00000000;
@@ -479,7 +477,8 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
                ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_MODE_CNTL_1] = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_PRIM_FILTER_CNTL] = 0;
                ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL] = 0x00000000;
-               ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL] = 0x00000000;
+               ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL__VS] = 0x00000000;
+               ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL__CL] = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_CLIP_CNTL] = 0x00090000;
                ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_BINNER_CNTL_0] = 0x00000003;
                ctx->tracked_regs.reg_value[SI_TRACKED_DB_DFSM_CONTROL] = 0x00000000;
@@ -490,6 +489,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
                ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET] = 0;
                ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_VTX_CNTL] = 0x00000005;
                ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_CLIPRECT_RULE]     = 0xffff;
+               ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_STIPPLE]      = 0;
                ctx->tracked_regs.reg_value[SI_TRACKED_VGT_ESGS_RING_ITEMSIZE]  = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_1]  = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_2]  = 0x00000000;
@@ -507,6 +507,9 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
                ctx->tracked_regs.reg_value[SI_TRACKED_VGT_PRIMITIVEID_EN]  = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_VGT_REUSE_OFF]  = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_SPI_VS_OUT_CONFIG]  = 0x00000000;
+               ctx->tracked_regs.reg_value[SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP]  = 0x00000000;
+               ctx->tracked_regs.reg_value[SI_TRACKED_GE_NGG_SUBGRP_CNTL]  = 0x00000000;
+               ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_IDX_FORMAT]  = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_POS_FORMAT]  = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VTE_CNTL]  = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_NGG_CNTL]  = 0x00000000;
@@ -520,11 +523,13 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
                ctx->tracked_regs.reg_value[SI_TRACKED_VGT_TF_PARAM]  = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL]  = 0x0000001e; /* From GFX8 */
 
-               /* Set all saved registers state to saved. */
+               /* Set all cleared context registers to saved. */
                ctx->tracked_regs.reg_saved = 0xffffffffffffffff;
+               ctx->last_gs_out_prim = 0; /* cleared by CLEAR_STATE */
        } else {
                /* Set all saved registers state to unknown. */
                ctx->tracked_regs.reg_saved = 0;
+               ctx->last_gs_out_prim = -1; /* unknown */
        }
 
        /* 0xffffffff is a impossible value to register SPI_PS_INPUT_CNTL_n */