{
struct radeon_cmdbuf *cs = ctx->gfx_cs;
struct radeon_winsys *ws = ctx->ws;
+ struct si_screen *sscreen = ctx->screen;
const unsigned wait_ps_cs = SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
unsigned wait_flags = 0;
if (ctx->gfx_flush_in_progress)
return;
- if (!ctx->screen->info.kernel_flushes_tc_l2_after_ib) {
+ /* The amdgpu kernel driver synchronizes execution for shared DMABUFs between
+ * processes on DRM >= 3.39.0, so we don't have to wait at the end of IBs to
+ * make sure everything is idle.
+ *
+ * The amdgpu winsys synchronizes execution for buffers shared by different
+ * contexts within the same process.
+ *
+ * Interop with AMDVLK, RADV, or OpenCL within the same process requires
+ * explicit fences or glFinish.
+ */
+ if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 39)
+ flags |= RADEON_FLUSH_START_NEXT_GFX_IB_NOW;
+
+ if (!sscreen->info.kernel_flushes_tc_l2_after_ib) {
wait_flags |= wait_ps_cs | SI_CONTEXT_INV_L2;
} else if (ctx->chip_class == GFX6) {
/* The kernel flushes L2 before shaders are finished. */
if (ctx->b.get_device_reset_status(&ctx->b) != PIPE_NO_RESET)
return;
- if (ctx->screen->debug_flags & DBG(CHECK_VM))
+ if (sscreen->debug_flags & DBG(CHECK_VM))
flags &= ~PIPE_FLUSH_ASYNC;
ctx->gfx_flush_in_progress = true;
- /* If the gallium frontend is flushing the GFX IB, si_flush_from_st is
+ /* If the gallium frontend is flushing the GFX IB, si_flush_from_st is
* responsible for flushing the DMA IB and merging the fences from both.
* If the driver flushes the GFX IB internally, and it should never ask
* for a fence handle.
* idle when we leave the IB, otherwise another process
* might overwrite it while our shaders are busy.
*/
- if (ctx->screen->use_ngg_streamout)
+ if (sscreen->use_ngg_streamout)
wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
}
}
}
/* Check VM faults if needed. */
- if (ctx->screen->debug_flags & DBG(CHECK_VM)) {
+ if (sscreen->debug_flags & DBG(CHECK_VM)) {
/* Use conservative timeout 800ms, after which we won't wait any
* longer and assume the GPU is hung.
*/
if (ctx->current_saved_cs)
si_saved_cs_reference(&ctx->current_saved_cs, NULL);
- si_begin_new_gfx_cs(ctx);
+ si_begin_new_gfx_cs(ctx, false);
ctx->gfx_flush_in_progress = false;
}
ctx->tracked_regs.reg_value[SI_TRACKED_SX_PS_DOWNCONVERT] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_SX_BLEND_OPT_EPSILON] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_SX_BLEND_OPT_CONTROL] = 0x00000000;
- ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_CNTL] = 0x00001000;
- ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_AA_CONFIG] = 0x00000000;
- ctx->tracked_regs.reg_value[SI_TRACKED_DB_EQAA] = 0x00000000;
+ ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_CNTL] = 0x00001000;
+ ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_AA_CONFIG] = 0x00000000;
+ ctx->tracked_regs.reg_value[SI_TRACKED_DB_EQAA] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_MODE_CNTL_1] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_PRIM_FILTER_CNTL] = 0;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL__VS] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL__CL] = 0x00000000;
- ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_CLIP_CNTL] = 0x00090000;
+ ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_CLIP_CNTL] = 0x00090000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_BINNER_CNTL_0] = 0x00000003;
- ctx->tracked_regs.reg_value[SI_TRACKED_DB_DFSM_CONTROL] = 0x00000000;
- ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ] = 0x3f800000;
- ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ] = 0x3f800000;
- ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ] = 0x3f800000;
- ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ] = 0x3f800000;
+ ctx->tracked_regs.reg_value[SI_TRACKED_DB_DFSM_CONTROL] = 0x00000000;
+ ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ] = 0x3f800000;
+ ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ] = 0x3f800000;
+ ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ] = 0x3f800000;
+ ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ] = 0x3f800000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET] = 0;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_VTX_CNTL] = 0x00000005;
- ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_CLIPRECT_RULE] = 0xffff;
- ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_STIPPLE] = 0;
+ ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_CLIPRECT_RULE] = 0xffff;
+ ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_STIPPLE] = 0;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_ESGS_RING_ITEMSIZE] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_1] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_2] = 0x00000000;
ctx->last_gs_out_prim = 0; /* cleared by CLEAR_STATE */
}
-void si_begin_new_gfx_cs(struct si_context *ctx)
+void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
{
if (ctx->is_debug)
si_begin_gfx_cs_debug(ctx);
ctx->flags |= SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE |
SI_CONTEXT_INV_L2 | SI_CONTEXT_START_PIPELINE_STATS;
- ctx->cs_shader_state.initialized = false;
+ radeon_add_to_buffer_list(ctx, ctx->gfx_cs, ctx->border_color_buffer,
+ RADEON_USAGE_READ, RADEON_PRIO_BORDER_COLORS);
+ if (ctx->shadowed_regs) {
+ radeon_add_to_buffer_list(ctx, ctx->gfx_cs, ctx->shadowed_regs,
+ RADEON_USAGE_READWRITE,
+ RADEON_PRIO_DESCRIPTORS);
+ }
+
si_add_all_descriptors_to_bo_list(ctx);
- si_shader_pointers_mark_dirty(ctx);
+
+ if (first_cs || !ctx->shadowed_regs) {
+ si_shader_pointers_mark_dirty(ctx);
+ ctx->cs_shader_state.initialized = false;
+ }
if (!ctx->has_graphics) {
ctx->initial_gfx_cs_size = ctx->gfx_cs->current.cdw;
return;
}
+ if (ctx->tess_rings) {
+ radeon_add_to_buffer_list(ctx, ctx->gfx_cs, si_resource(ctx->tess_rings),
+ RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
+ }
+
/* set all valid group as dirty so they get reemited on
* next draw command
*/
- si_pm4_reset_emitted(ctx);
+ si_pm4_reset_emitted(ctx, first_cs);
/* The CS initialization should be emitted before everything else. */
- si_pm4_emit(ctx, ctx->init_config);
- if (ctx->init_config_gs_rings)
- si_pm4_emit(ctx, ctx->init_config_gs_rings);
+ if (ctx->cs_preamble_state)
+ si_pm4_emit(ctx, ctx->cs_preamble_state);
+ if (ctx->cs_preamble_gs_rings)
+ si_pm4_emit(ctx, ctx->cs_preamble_gs_rings);
if (ctx->queued.named.ls)
ctx->prefetch_L2_mask |= SI_PREFETCH_LS;
/* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
bool has_clear_state = ctx->screen->info.has_clear_state;
- if (has_clear_state) {
- ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs);
+ if (has_clear_state || ctx->shadowed_regs) {
+ ctx->framebuffer.dirty_cbufs =
+ u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs);
/* CLEAR_STATE disables the zbuffer, so only enable it if it's bound. */
ctx->framebuffer.dirty_zsbuf = ctx->framebuffer.state.zsbuf != NULL;
} else {
ctx->framebuffer.dirty_zsbuf = true;
}
/* This should always be marked as dirty to set the framebuffer scissor
- * at least. */
+ * at least.
+ *
+ * Even with shadowed registers, we have to add buffers to the buffer list.
+ * All of these do that.
+ */
si_mark_atom_dirty(ctx, &ctx->atoms.s.framebuffer);
-
- si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_regs);
- /* CLEAR_STATE sets zeros. */
- if (!has_clear_state || ctx->clip_state.any_nonzeros)
- si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_state);
- ctx->sample_locs_num_samples = 0;
- si_mark_atom_dirty(ctx, &ctx->atoms.s.msaa_sample_locs);
- si_mark_atom_dirty(ctx, &ctx->atoms.s.msaa_config);
- /* CLEAR_STATE sets 0xffff. */
- if (!has_clear_state || ctx->sample_mask != 0xffff)
- si_mark_atom_dirty(ctx, &ctx->atoms.s.sample_mask);
- si_mark_atom_dirty(ctx, &ctx->atoms.s.cb_render_state);
- /* CLEAR_STATE sets zeros. */
- if (!has_clear_state || ctx->blend_color.any_nonzeros)
- si_mark_atom_dirty(ctx, &ctx->atoms.s.blend_color);
- si_mark_atom_dirty(ctx, &ctx->atoms.s.db_render_state);
- if (ctx->chip_class >= GFX9)
- si_mark_atom_dirty(ctx, &ctx->atoms.s.dpbb_state);
- si_mark_atom_dirty(ctx, &ctx->atoms.s.stencil_ref);
- si_mark_atom_dirty(ctx, &ctx->atoms.s.spi_map);
- if (!ctx->screen->use_ngg_streamout)
- si_mark_atom_dirty(ctx, &ctx->atoms.s.streamout_enable);
si_mark_atom_dirty(ctx, &ctx->atoms.s.render_cond);
- /* CLEAR_STATE disables all window rectangles. */
- if (!has_clear_state || ctx->num_window_rectangles > 0)
- si_mark_atom_dirty(ctx, &ctx->atoms.s.window_rectangles);
-
- si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
- si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
+ if (first_cs || !ctx->shadowed_regs) {
+ /* These don't add any buffers, so skip them with shadowing. */
+ si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_regs);
+ /* CLEAR_STATE sets zeros. */
+ if (!has_clear_state || ctx->clip_state.any_nonzeros)
+ si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_state);
+ ctx->sample_locs_num_samples = 0;
+ si_mark_atom_dirty(ctx, &ctx->atoms.s.msaa_sample_locs);
+ si_mark_atom_dirty(ctx, &ctx->atoms.s.msaa_config);
+ /* CLEAR_STATE sets 0xffff. */
+ if (!has_clear_state || ctx->sample_mask != 0xffff)
+ si_mark_atom_dirty(ctx, &ctx->atoms.s.sample_mask);
+ si_mark_atom_dirty(ctx, &ctx->atoms.s.cb_render_state);
+ /* CLEAR_STATE sets zeros. */
+ if (!has_clear_state || ctx->blend_color.any_nonzeros)
+ si_mark_atom_dirty(ctx, &ctx->atoms.s.blend_color);
+ si_mark_atom_dirty(ctx, &ctx->atoms.s.db_render_state);
+ if (ctx->chip_class >= GFX9)
+ si_mark_atom_dirty(ctx, &ctx->atoms.s.dpbb_state);
+ si_mark_atom_dirty(ctx, &ctx->atoms.s.stencil_ref);
+ si_mark_atom_dirty(ctx, &ctx->atoms.s.spi_map);
+ if (!ctx->screen->use_ngg_streamout)
+ si_mark_atom_dirty(ctx, &ctx->atoms.s.streamout_enable);
+ /* CLEAR_STATE disables all window rectangles. */
+ if (!has_clear_state || ctx->num_window_rectangles > 0)
+ si_mark_atom_dirty(ctx, &ctx->atoms.s.window_rectangles);
+ si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
+ si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
+
+ /* Invalidate various draw states so that they are emitted before
+ * the first draw call. */
+ si_invalidate_draw_sh_constants(ctx);
+ ctx->last_index_size = -1;
+ ctx->last_primitive_restart_en = -1;
+ ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
+ ctx->last_prim = -1;
+ ctx->last_multi_vgt_param = -1;
+ ctx->last_vs_state = ~0;
+ ctx->last_ls = NULL;
+ ctx->last_tcs = NULL;
+ ctx->last_tes_sh_base = -1;
+ ctx->last_num_tcs_input_cp = -1;
+ ctx->last_ls_hs_config = -1; /* impossible value */
+ ctx->last_binning_enabled = -1;
+
+ if (has_clear_state) {
+ si_set_tracked_regs_to_clear_state(ctx);
+ } else {
+ /* Set all register values to unknown. */
+ ctx->tracked_regs.reg_saved = 0;
+ ctx->last_gs_out_prim = -1; /* unknown */
+ }
+
+ /* 0xffffffff is an impossible value to register SPI_PS_INPUT_CNTL_n */
+ memset(ctx->tracked_regs.spi_ps_input_cntl, 0xff, sizeof(uint32_t) * 32);
+ }
+
si_mark_atom_dirty(ctx, &ctx->atoms.s.scratch_state);
if (ctx->scratch_buffer) {
si_context_add_resource_size(ctx, &ctx->scratch_buffer->b.b);
assert(!ctx->gfx_cs->prev_dw);
ctx->initial_gfx_cs_size = ctx->gfx_cs->current.cdw;
-
- /* Invalidate various draw states so that they are emitted before
- * the first draw call. */
- si_invalidate_draw_sh_constants(ctx);
- ctx->last_index_size = -1;
- ctx->last_primitive_restart_en = -1;
- ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
- ctx->last_prim = -1;
- ctx->last_multi_vgt_param = -1;
- ctx->last_vs_state = ~0;
- ctx->last_ls = NULL;
- ctx->last_tcs = NULL;
- ctx->last_tes_sh_base = -1;
- ctx->last_num_tcs_input_cp = -1;
- ctx->last_ls_hs_config = -1; /* impossible value */
- ctx->last_binning_enabled = -1;
ctx->small_prim_cull_info_dirty = ctx->small_prim_cull_info_buf != NULL;
-
ctx->prim_discard_compute_ib_initialized = false;
/* Compute-based primitive discard:
ctx->index_ring_base = ctx->index_ring_size_per_ib;
ctx->index_ring_offset = 0;
-
- if (has_clear_state) {
- si_set_tracked_regs_to_clear_state(ctx);
- } else {
- /* Set all register values to unknown. */
- ctx->tracked_regs.reg_saved = 0;
- ctx->last_gs_out_prim = -1; /* unknown */
- }
-
- /* 0xffffffff is a impossible value to register SPI_PS_INPUT_CNTL_n */
- memset(ctx->tracked_regs.spi_ps_input_cntl, 0xff, sizeof(uint32_t) * 32);
}
projects / mesa.git / blobdiff