* Authors:
* Jerome Glisse
*/
-#include "../radeon/r600_cs.h"
-#include "sid.h"
-#include "si_pm4.h"
-#include "si_pipe.h"
-#include "util/u_memory.h"
-#include <errno.h>
+#include "si_pipe.h"
/* initialize */
void si_need_cs_space(struct si_context *ctx, unsigned num_dw,
num_dw += ctx->atoms.cache_flush->num_dw;
#if SI_TRACE_CS
- if (ctx->screen->trace_bo) {
+ if (ctx->screen->b.trace_bo) {
num_dw += SI_TRACE_CS_DWORDS;
}
#endif
{
struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
- if (!cs->cdw)
+ if (cs->cdw == ctx->b.initial_gfx_cs_size)
return;
/* suspend queries */
R600_CONTEXT_FLUSH_AND_INV_CB_META |
R600_CONTEXT_FLUSH_AND_INV_DB |
R600_CONTEXT_FLUSH_AND_INV_DB_META |
- R600_CONTEXT_INV_TEX_CACHE;
+ R600_CONTEXT_INV_TEX_CACHE |
+ /* this is probably not needed anymore */
+ R600_CONTEXT_PS_PARTIAL_FLUSH;
si_emit_cache_flush(&ctx->b, NULL);
- /* this is probably not needed anymore */
- cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
- cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
-
/* force to keep tiling flags */
flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
#if SI_TRACE_CS
- if (ctx->screen->trace_bo) {
+ if (ctx->screen->b.trace_bo) {
struct si_screen *sscreen = ctx->screen;
unsigned i;
for (i = 0; i < cs->cdw; i++) {
- fprintf(stderr, "[%4d] [%5d] 0x%08x\n", sscreen->cs_count, i, cs->buf[i]);
+ fprintf(stderr, "[%4d] [%5d] 0x%08x\n", sscreen->b.cs_count, i, cs->buf[i]);
}
- sscreen->cs_count++;
+ sscreen->b.cs_count++;
}
#endif
ctx->b.ws->cs_flush(ctx->b.rings.gfx.cs, flags, 0);
#if SI_TRACE_CS
- if (ctx->screen->trace_bo) {
+ if (ctx->screen->b.trace_bo) {
struct si_screen *sscreen = ctx->screen;
unsigned i;
for (i = 0; i < 10; i++) {
usleep(5);
- if (!ctx->ws->buffer_is_busy(sscreen->trace_bo->buf, RADEON_USAGE_READWRITE)) {
+ if (!ctx->ws->buffer_is_busy(sscreen->b.trace_bo->buf, RADEON_USAGE_READWRITE)) {
break;
}
}
if (i == 10) {
fprintf(stderr, "timeout on cs lockup likely happen at cs %d dw %d\n",
- sscreen->trace_ptr[1], sscreen->trace_ptr[0]);
+ sscreen->b.trace_ptr[1], sscreen->b.trace_ptr[0]);
} else {
- fprintf(stderr, "cs %d executed in %dms\n", sscreen->trace_ptr[1], i * 5);
+ fprintf(stderr, "cs %d executed in %dms\n", sscreen->b.trace_ptr[1], i * 5);
}
}
#endif
r600_resume_nontimer_queries(&ctx->b);
}
+ ctx->framebuffer.atom.dirty = true;
si_all_descriptors_begin_new_cs(ctx);
+
+ ctx->b.initial_gfx_cs_size = ctx->b.rings.gfx.cs->cdw;
}
#if SI_TRACE_CS
struct radeon_winsys_cs *cs = sctx->cs;
uint64_t va;
- va = r600_resource_va(&sscreen->screen, (void*)sscreen->trace_bo);
- r600_context_bo_reloc(sctx, sscreen->trace_bo, RADEON_USAGE_READWRITE);
+ va = r600_resource_va(&sscreen->screen, (void*)sscreen->b.trace_bo);
+ r600_context_bo_reloc(sctx, sscreen->b.trace_bo, RADEON_USAGE_READWRITE);
cs->buf[cs->cdw++] = PKT3(PKT3_WRITE_DATA, 4, 0);
cs->buf[cs->cdw++] = PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) |
PKT3_WRITE_DATA_WR_CONFIRM |
cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL;
cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFFFFFFFUL;
cs->buf[cs->cdw++] = cs->cdw;
- cs->buf[cs->cdw++] = sscreen->cs_count;
+ cs->buf[cs->cdw++] = sscreen->b.cs_count;
}
#endif