* Authors:
* Jerome Glisse
*/
-#include "../radeon/r600_cs.h"
-#include "sid.h"
-#include "si_pm4.h"
-#include "si_pipe.h"
-#include "util/u_memory.h"
-#include <errno.h>
+#include "si_pipe.h"
/* initialize */
void si_need_cs_space(struct si_context *ctx, unsigned num_dw,
{
struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
- if (!cs->cdw)
+ if (cs->cdw == ctx->b.initial_gfx_cs_size)
return;
/* suspend queries */
R600_CONTEXT_FLUSH_AND_INV_CB_META |
R600_CONTEXT_FLUSH_AND_INV_DB |
R600_CONTEXT_FLUSH_AND_INV_DB_META |
- R600_CONTEXT_INV_TEX_CACHE;
+ R600_CONTEXT_INV_TEX_CACHE |
+ /* this is probably not needed anymore */
+ R600_CONTEXT_PS_PARTIAL_FLUSH;
si_emit_cache_flush(&ctx->b, NULL);
- /* this is probably not needed anymore */
- cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
- cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
-
/* force to keep tiling flags */
flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
r600_resume_nontimer_queries(&ctx->b);
}
+ ctx->framebuffer.atom.dirty = true;
si_all_descriptors_begin_new_cs(ctx);
+
+ ctx->b.initial_gfx_cs_size = ctx->b.rings.gfx.cs->cdw;
}
#if SI_TRACE_CS