radeonsi: move gfx fence wait out of si_check_vm_faults

[mesa.git] / src / gallium / drivers / radeonsi / si_hw_context.c

diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index 6221f1cb83a5c9ae199c36101cd20005fdec54bd..656d435361c4eb4a2d0c8921428727c9e1256e33 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -84,9 +84,8 @@ void si_need_cs_space(struct si_context *ctx)
        /* If the CS is sufficiently large, don't count the space needed
         * and just flush if there is not enough space left.
         */
-       if (unlikely(cs->cdw > cs->max_dw - 2048 ||
-                     (ce_ib && ce_ib->max_dw - ce_ib->cdw <
-                      si_ce_needed_cs_space())))
+       if (!ctx->b.ws->cs_check_space(cs, 2048) ||
+           (ce_ib && !ctx->b.ws->cs_check_space(ce_ib, si_ce_needed_cs_space())))
                ctx->b.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
 }
 
@@ -131,26 +130,11 @@ void si_context_gfx_flush(void *context, unsigned flags,
                si_trace_emit(ctx);
 
        if (ctx->is_debug) {
-               unsigned i;
-
                /* Save the IB for debug contexts. */
-               free(ctx->last_ib);
-               ctx->last_ib_dw_size = cs->cdw;
-               ctx->last_ib = malloc(cs->cdw * 4);
-               memcpy(ctx->last_ib, cs->buf, cs->cdw * 4);
+               radeon_clear_saved_cs(&ctx->last_gfx);
+               radeon_save_cs(ws, cs, &ctx->last_gfx);
                r600_resource_reference(&ctx->last_trace_buf, ctx->trace_buf);
                r600_resource_reference(&ctx->trace_buf, NULL);
-
-               /* Save the buffer list. */
-               if (ctx->last_bo_list) {
-                       for (i = 0; i < ctx->last_bo_count; i++)
-                               pb_reference(&ctx->last_bo_list[i].buf, NULL);
-                       free(ctx->last_bo_list);
-               }
-               ctx->last_bo_count = ws->cs_get_buffer_list(cs, NULL);
-               ctx->last_bo_list = calloc(ctx->last_bo_count,
-                                          sizeof(ctx->last_bo_list[0]));
-               ws->cs_get_buffer_list(cs, ctx->last_bo_list);
        }
 
        /* Flush the CS. */
@@ -160,8 +144,14 @@ void si_context_gfx_flush(void *context, unsigned flags,
                ws->fence_reference(fence, ctx->last_gfx_fence);
 
        /* Check VM faults if needed. */
-       if (ctx->screen->b.debug_flags & DBG_CHECK_VM)
+       if (ctx->screen->b.debug_flags & DBG_CHECK_VM) {
+               /* Use conservative timeout 800ms, after which we won't wait any
+                * longer and assume the GPU is hung.
+                */
+               ctx->b.ws->fence_wait(ctx->b.ws, ctx->last_gfx_fence, 800*1000*1000);
+
                si_check_vm_faults(ctx);
+       }
 
        si_begin_new_cs(ctx);
        ctx->gfx_flush_in_progress = false;
@@ -208,6 +198,9 @@ void si_begin_new_cs(struct si_context *ctx)
        else if (ctx->ce_ib)
                si_ce_enable_loads(ctx->ce_ib);
 
+       if (ctx->ce_preamble_ib)
+               si_ce_reinitialize_all_descriptors(ctx);
+
        ctx->framebuffer.dirty_cbufs = (1 << 8) - 1;
        ctx->framebuffer.dirty_zsbuf = true;
        si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
@@ -233,7 +226,8 @@ void si_begin_new_cs(struct si_context *ctx)
 
        r600_postflush_resume_features(&ctx->b);
 
-       ctx->b.initial_gfx_cs_size = ctx->b.gfx.cs->cdw;
+       assert(!ctx->b.gfx.cs->prev_dw);
+       ctx->b.initial_gfx_cs_size = ctx->b.gfx.cs->current.cdw;
 
        /* Invalidate various draw states so that they are emitted before
         * the first draw call. */