radeonsi: Don't modify PA_SC_RASTER_CONFIG register value if rb_mask == 0

[mesa.git] / src / gallium / drivers / radeonsi / si_hw_context.c

diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index 185041e959848414ce6b3e37e105fa6c528d302f..983a0976b044ce344acf4154ef6a2090181b9c62 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -35,15 +35,15 @@ void si_need_cs_space(struct si_context *ctx, unsigned num_dw,
        /* The number of dwords we already used in the CS so far. */
        num_dw += ctx->b.rings.gfx.cs->cdw;
 
-       for (i = 0; i < SI_NUM_ATOMS(ctx); i++) {
-               if (ctx->atoms.array[i]->dirty) {
-                       num_dw += ctx->atoms.array[i]->num_dw;
+       if (count_draw_in) {
+               for (i = 0; i < SI_NUM_ATOMS(ctx); i++) {
+                       if (ctx->atoms.array[i]->dirty) {
+                               num_dw += ctx->atoms.array[i]->num_dw;
+                       }
                }
-       }
 
-       if (count_draw_in) {
                /* The number of dwords all the dirty states would take. */
-               num_dw += ctx->pm4_dirty_cdwords;
+               num_dw += si_pm4_dirty_dw(ctx);
 
                /* The upper-bound of how much a draw command would take. */
                num_dw += SI_MAX_DRAW_CS_DWORDS;
@@ -63,7 +63,7 @@ void si_need_cs_space(struct si_context *ctx, unsigned num_dw,
        }
 
        /* Count in framebuffer cache flushes at the end of CS. */
-       num_dw += ctx->atoms.cache_flush->num_dw;
+       num_dw += ctx->atoms.s.cache_flush->num_dw;
 
 #if SI_TRACE_CS
        if (ctx->screen->b.trace_bo) {
@@ -83,7 +83,7 @@ void si_context_gfx_flush(void *context, unsigned flags,
        struct si_context *ctx = context;
        struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
 
-       if (cs->cdw == ctx->b.initial_gfx_cs_size)
+       if (cs->cdw == ctx->b.initial_gfx_cs_size && !fence)
                return;
 
        ctx->b.rings.gfx.flushing = true;
@@ -102,20 +102,8 @@ void si_context_gfx_flush(void *context, unsigned flags,
        /* force to keep tiling flags */
        flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
 
-#if SI_TRACE_CS
-       if (ctx->screen->b.trace_bo) {
-               struct si_screen *sscreen = ctx->screen;
-               unsigned i;
-
-               for (i = 0; i < cs->cdw; i++) {
-                       fprintf(stderr, "[%4d] [%5d] 0x%08x\n", sscreen->b.cs_count, i, cs->buf[i]);
-               }
-               sscreen->b.cs_count++;
-       }
-#endif
-
        /* Flush the CS. */
-       ctx->b.ws->cs_flush(cs, flags, fence, 0);
+       ctx->b.ws->cs_flush(cs, flags, fence, ctx->screen->b.cs_count++);
        ctx->b.rings.gfx.flushing = false;
 
 #if SI_TRACE_CS
@@ -125,7 +113,7 @@ void si_context_gfx_flush(void *context, unsigned flags,
 
                for (i = 0; i < 10; i++) {
                        usleep(5);
-                       if (!ctx->ws->buffer_is_busy(sscreen->b.trace_bo->buf, RADEON_USAGE_READWRITE)) {
+                       if (!ctx->b.ws->buffer_is_busy(sscreen->b.trace_bo->buf, RADEON_USAGE_READWRITE)) {
                                break;
                        }
                }
@@ -143,8 +131,6 @@ void si_context_gfx_flush(void *context, unsigned flags,
 
 void si_begin_new_cs(struct si_context *ctx)
 {
-       ctx->pm4_dirty_cdwords = 0;
-
        /* Flush read caches at the beginning of CS. */
        ctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
                        R600_CONTEXT_INV_CONST_CACHE |
@@ -159,31 +145,21 @@ void si_begin_new_cs(struct si_context *ctx)
        si_pm4_emit(ctx, ctx->queued.named.init);
        ctx->emitted.named.init = ctx->queued.named.init;
 
+       ctx->clip_regs.dirty = true;
        ctx->framebuffer.atom.dirty = true;
+       ctx->msaa_config.dirty = true;
+       ctx->db_render_state.dirty = true;
        ctx->b.streamout.enable_atom.dirty = true;
        si_all_descriptors_begin_new_cs(ctx);
 
        r600_postflush_resume_features(&ctx->b);
 
        ctx->b.initial_gfx_cs_size = ctx->b.rings.gfx.cs->cdw;
+       si_invalidate_draw_sh_constants(ctx);
+       ctx->last_primitive_restart_en = -1;
+       ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
+       ctx->last_gs_out_prim = -1;
+       ctx->last_prim = -1;
+       ctx->last_multi_vgt_param = -1;
+       ctx->last_rast_prim = -1;
 }
-
-#if SI_TRACE_CS
-void si_trace_emit(struct si_context *sctx)
-{
-       struct si_screen *sscreen = sctx->screen;
-       struct radeon_winsys_cs *cs = sctx->cs;
-       uint64_t va;
-
-       va = r600_resource_va(&sscreen->screen, (void*)sscreen->b.trace_bo);
-       r600_context_bo_reloc(sctx, sscreen->b.trace_bo, RADEON_USAGE_READWRITE);
-       cs->buf[cs->cdw++] = PKT3(PKT3_WRITE_DATA, 4, 0);
-       cs->buf[cs->cdw++] = PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) |
-                               PKT3_WRITE_DATA_WR_CONFIRM |
-                               PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME);
-       cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL;
-       cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFFFFFFFUL;
-       cs->buf[cs->cdw++] = cs->cdw;
-       cs->buf[cs->cdw++] = sscreen->b.cs_count;
-}
-#endif