freedreno/a3xx: only emit dirty consts
[mesa.git] / src / gallium / drivers / radeonsi / si_hw_context.c
index 37ca290291f490313a2ed965b4424fb7f1ad642d..e030c753d6cfc278efb403efca0b8ef78232c7eb 100644 (file)
@@ -35,13 +35,13 @@ void si_need_cs_space(struct si_context *ctx, unsigned num_dw,
        /* The number of dwords we already used in the CS so far. */
        num_dw += ctx->b.rings.gfx.cs->cdw;
 
-       for (i = 0; i < SI_NUM_ATOMS(ctx); i++) {
-               if (ctx->atoms.array[i]->dirty) {
-                       num_dw += ctx->atoms.array[i]->num_dw;
+       if (count_draw_in) {
+               for (i = 0; i < SI_NUM_ATOMS(ctx); i++) {
+                       if (ctx->atoms.array[i]->dirty) {
+                               num_dw += ctx->atoms.array[i]->num_dw;
+                       }
                }
-       }
 
-       if (count_draw_in) {
                /* The number of dwords all the dirty states would take. */
                num_dw += ctx->pm4_dirty_cdwords;
 
@@ -63,7 +63,7 @@ void si_need_cs_space(struct si_context *ctx, unsigned num_dw,
        }
 
        /* Count in framebuffer cache flushes at the end of CS. */
-       num_dw += ctx->atoms.cache_flush->num_dw;
+       num_dw += ctx->atoms.s.cache_flush->num_dw;
 
 #if SI_TRACE_CS
        if (ctx->screen->b.trace_bo) {
@@ -83,35 +83,12 @@ void si_context_gfx_flush(void *context, unsigned flags,
        struct si_context *ctx = context;
        struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
 
-       if (cs->cdw == ctx->b.initial_gfx_cs_size)
+       if (cs->cdw == ctx->b.initial_gfx_cs_size && !fence)
                return;
 
        ctx->b.rings.gfx.flushing = true;
 
-       /* Disable render condition. */
-       ctx->b.saved_render_cond = NULL;
-       ctx->b.saved_render_cond_cond = FALSE;
-       ctx->b.saved_render_cond_mode = 0;
-       if (ctx->b.current_render_cond) {
-               ctx->b.saved_render_cond = ctx->b.current_render_cond;
-               ctx->b.saved_render_cond_cond = ctx->b.current_render_cond_cond;
-               ctx->b.saved_render_cond_mode = ctx->b.current_render_cond_mode;
-               ctx->b.b.render_condition(&ctx->b.b, NULL, FALSE, 0);
-       }
-
-       /* suspend queries */
-       ctx->b.nontimer_queries_suspended = false;
-       if (ctx->b.num_cs_dw_nontimer_queries_suspend) {
-               r600_suspend_nontimer_queries(&ctx->b);
-               ctx->b.nontimer_queries_suspended = true;
-       }
-
-       ctx->b.streamout.suspended = false;
-
-       if (ctx->b.streamout.begin_emitted) {
-               r600_emit_streamout_end(&ctx->b);
-               ctx->b.streamout.suspended = true;
-       }
+       r600_preflush_suspend_features(&ctx->b);
 
        ctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
                        R600_CONTEXT_FLUSH_AND_INV_CB_META |
@@ -125,20 +102,8 @@ void si_context_gfx_flush(void *context, unsigned flags,
        /* force to keep tiling flags */
        flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
 
-#if SI_TRACE_CS
-       if (ctx->screen->b.trace_bo) {
-               struct si_screen *sscreen = ctx->screen;
-               unsigned i;
-
-               for (i = 0; i < cs->cdw; i++) {
-                       fprintf(stderr, "[%4d] [%5d] 0x%08x\n", sscreen->b.cs_count, i, cs->buf[i]);
-               }
-               sscreen->b.cs_count++;
-       }
-#endif
-
        /* Flush the CS. */
-       ctx->b.ws->cs_flush(cs, flags, fence, 0);
+       ctx->b.ws->cs_flush(cs, flags, fence, ctx->screen->b.cs_count++);
        ctx->b.rings.gfx.flushing = false;
 
 #if SI_TRACE_CS
@@ -148,7 +113,7 @@ void si_context_gfx_flush(void *context, unsigned flags,
 
                for (i = 0; i < 10; i++) {
                        usleep(5);
-                       if (!ctx->ws->buffer_is_busy(sscreen->b.trace_bo->buf, RADEON_USAGE_READWRITE)) {
+                       if (!ctx->b.ws->buffer_is_busy(sscreen->b.trace_bo->buf, RADEON_USAGE_READWRITE)) {
                                break;
                        }
                }
@@ -182,46 +147,13 @@ void si_begin_new_cs(struct si_context *ctx)
        si_pm4_emit(ctx, ctx->queued.named.init);
        ctx->emitted.named.init = ctx->queued.named.init;
 
-       if (ctx->b.streamout.suspended) {
-               ctx->b.streamout.append_bitmask = ctx->b.streamout.enabled_mask;
-               r600_streamout_buffers_dirty(&ctx->b);
-       }
-
-       /* resume queries */
-       if (ctx->b.nontimer_queries_suspended) {
-               r600_resume_nontimer_queries(&ctx->b);
-       }
-
-       /* Re-enable render condition. */
-       if (ctx->b.saved_render_cond) {
-               ctx->b.b.render_condition(&ctx->b.b, ctx->b.saved_render_cond,
-                                         ctx->b.saved_render_cond_cond,
-                                         ctx->b.saved_render_cond_mode);
-       }
-
        ctx->framebuffer.atom.dirty = true;
+       ctx->msaa_config.dirty = true;
+       ctx->db_render_state.dirty = true;
        ctx->b.streamout.enable_atom.dirty = true;
        si_all_descriptors_begin_new_cs(ctx);
 
-       ctx->b.initial_gfx_cs_size = ctx->b.rings.gfx.cs->cdw;
-}
+       r600_postflush_resume_features(&ctx->b);
 
-#if SI_TRACE_CS
-void si_trace_emit(struct si_context *sctx)
-{
-       struct si_screen *sscreen = sctx->screen;
-       struct radeon_winsys_cs *cs = sctx->cs;
-       uint64_t va;
-
-       va = r600_resource_va(&sscreen->screen, (void*)sscreen->b.trace_bo);
-       r600_context_bo_reloc(sctx, sscreen->b.trace_bo, RADEON_USAGE_READWRITE);
-       cs->buf[cs->cdw++] = PKT3(PKT3_WRITE_DATA, 4, 0);
-       cs->buf[cs->cdw++] = PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) |
-                               PKT3_WRITE_DATA_WR_CONFIRM |
-                               PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME);
-       cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL;
-       cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFFFFFFFUL;
-       cs->buf[cs->cdw++] = cs->cdw;
-       cs->buf[cs->cdw++] = sscreen->b.cs_count;
+       ctx->b.initial_gfx_cs_size = ctx->b.rings.gfx.cs->cdw;
 }
-#endif