* SOFTWARE.
*/
-#include "radeon/r600_cs.h"
-#include "radeon/r600_query.h"
+#include "si_build_pm4.h"
+#include "si_query.h"
#include "util/u_memory.h"
-#include "si_pipe.h"
-#include "sid.h"
enum si_pc_reg_layout {
/* All secondary selector dwords follow as one block after the primary
static struct si_pc_block_base cik_CB = {
.name = "CB",
.num_counters = 4,
- .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_INSTANCE_GROUPS,
+ .flags = SI_PC_BLOCK_SE | SI_PC_BLOCK_INSTANCE_GROUPS,
.select0 = R_037000_CB_PERFCOUNTER_FILTER,
.counter0_lo = R_035018_CB_PERFCOUNTER0_LO,
static struct si_pc_block_base cik_DB = {
.name = "DB",
.num_counters = 4,
- .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_INSTANCE_GROUPS,
+ .flags = SI_PC_BLOCK_SE | SI_PC_BLOCK_INSTANCE_GROUPS,
.select0 = R_037100_DB_PERFCOUNTER0_SELECT,
.counter0_lo = R_035100_DB_PERFCOUNTER0_LO,
static struct si_pc_block_base cik_PA_SC = {
.name = "PA_SC",
.num_counters = 8,
- .flags = R600_PC_BLOCK_SE,
+ .flags = SI_PC_BLOCK_SE,
.select0 = R_036500_PA_SC_PERFCOUNTER0_SELECT,
.counter0_lo = R_034500_PA_SC_PERFCOUNTER0_LO,
static struct si_pc_block_base cik_PA_SU = {
.name = "PA_SU",
.num_counters = 4,
- .flags = R600_PC_BLOCK_SE,
+ .flags = SI_PC_BLOCK_SE,
.select0 = R_036400_PA_SU_PERFCOUNTER0_SELECT,
.counter0_lo = R_034400_PA_SU_PERFCOUNTER0_LO,
static struct si_pc_block_base cik_SPI = {
.name = "SPI",
.num_counters = 6,
- .flags = R600_PC_BLOCK_SE,
+ .flags = SI_PC_BLOCK_SE,
.select0 = R_036600_SPI_PERFCOUNTER0_SELECT,
.counter0_lo = R_034604_SPI_PERFCOUNTER0_LO,
static struct si_pc_block_base cik_SQ = {
.name = "SQ",
.num_counters = 16,
- .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_SHADER,
+ .flags = SI_PC_BLOCK_SE | SI_PC_BLOCK_SHADER,
.select0 = R_036700_SQ_PERFCOUNTER0_SELECT,
.select_or = S_036700_SQC_BANK_MASK(15) |
static struct si_pc_block_base cik_SX = {
.name = "SX",
.num_counters = 4,
- .flags = R600_PC_BLOCK_SE,
+ .flags = SI_PC_BLOCK_SE,
.select0 = R_036900_SX_PERFCOUNTER0_SELECT,
.counter0_lo = R_034900_SX_PERFCOUNTER0_LO,
static struct si_pc_block_base cik_TA = {
.name = "TA",
.num_counters = 2,
- .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_INSTANCE_GROUPS | R600_PC_BLOCK_SHADER_WINDOWED,
+ .flags = SI_PC_BLOCK_SE | SI_PC_BLOCK_INSTANCE_GROUPS | SI_PC_BLOCK_SHADER_WINDOWED,
.select0 = R_036B00_TA_PERFCOUNTER0_SELECT,
.counter0_lo = R_034B00_TA_PERFCOUNTER0_LO,
static struct si_pc_block_base cik_TD = {
.name = "TD",
.num_counters = 2,
- .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_INSTANCE_GROUPS | R600_PC_BLOCK_SHADER_WINDOWED,
+ .flags = SI_PC_BLOCK_SE | SI_PC_BLOCK_INSTANCE_GROUPS | SI_PC_BLOCK_SHADER_WINDOWED,
.select0 = R_036C00_TD_PERFCOUNTER0_SELECT,
.counter0_lo = R_034C00_TD_PERFCOUNTER0_LO,
static struct si_pc_block_base cik_TCA = {
.name = "TCA",
.num_counters = 4,
- .flags = R600_PC_BLOCK_INSTANCE_GROUPS,
+ .flags = SI_PC_BLOCK_INSTANCE_GROUPS,
.select0 = R_036E40_TCA_PERFCOUNTER0_SELECT,
.counter0_lo = R_034E40_TCA_PERFCOUNTER0_LO,
static struct si_pc_block_base cik_TCC = {
.name = "TCC",
.num_counters = 4,
- .flags = R600_PC_BLOCK_INSTANCE_GROUPS,
+ .flags = SI_PC_BLOCK_INSTANCE_GROUPS,
.select0 = R_036E00_TCC_PERFCOUNTER0_SELECT,
.counter0_lo = R_034E00_TCC_PERFCOUNTER0_LO,
static struct si_pc_block_base cik_TCP = {
.name = "TCP",
.num_counters = 4,
- .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_INSTANCE_GROUPS | R600_PC_BLOCK_SHADER_WINDOWED,
+ .flags = SI_PC_BLOCK_SE | SI_PC_BLOCK_INSTANCE_GROUPS | SI_PC_BLOCK_SHADER_WINDOWED,
.select0 = R_036D00_TCP_PERFCOUNTER0_SELECT,
.counter0_lo = R_034D00_TCP_PERFCOUNTER0_LO,
static struct si_pc_block_base cik_VGT = {
.name = "VGT",
.num_counters = 4,
- .flags = R600_PC_BLOCK_SE,
+ .flags = SI_PC_BLOCK_SE,
.select0 = R_036230_VGT_PERFCOUNTER0_SELECT,
.counter0_lo = R_034240_VGT_PERFCOUNTER0_LO,
* blocks here matters.
*/
static struct si_pc_block groups_CIK[] = {
- { &cik_CB, 226, 4 },
+ { &cik_CB, 226},
{ &cik_CPF, 17 },
- { &cik_DB, 257, 4 },
+ { &cik_DB, 257},
{ &cik_GRBM, 34 },
{ &cik_GRBMSE, 15 },
{ &cik_PA_SU, 153 },
{ &cik_SX, 32 },
{ &cik_TA, 111, 11 },
{ &cik_TCA, 39, 2 },
- { &cik_TCC, 160, 16 },
+ { &cik_TCC, 160},
{ &cik_TD, 55, 11 },
{ &cik_TCP, 154, 11 },
{ &cik_GDS, 121 },
};
static struct si_pc_block groups_VI[] = {
- { &cik_CB, 405, 4 },
+ { &cik_CB, 405},
{ &cik_CPF, 19 },
- { &cik_DB, 257, 4 },
+ { &cik_DB, 257},
{ &cik_GRBM, 34 },
{ &cik_GRBMSE, 15 },
{ &cik_PA_SU, 153 },
{ &cik_SX, 34 },
{ &cik_TA, 119, 16 },
{ &cik_TCA, 35, 2 },
- { &cik_TCC, 192, 16 },
+ { &cik_TCC, 192},
{ &cik_TD, 55, 16 },
{ &cik_TCP, 180, 16 },
{ &cik_GDS, 121 },
};
static struct si_pc_block groups_gfx9[] = {
- { &cik_CB, 438, 4 },
+ { &cik_CB, 438},
{ &cik_CPF, 32 },
- { &cik_DB, 328, 4 },
+ { &cik_DB, 328},
{ &cik_GRBM, 38 },
{ &cik_GRBMSE, 16 },
{ &cik_PA_SU, 292 },
{ &cik_SX, 208 },
{ &cik_TA, 119, 16 },
{ &cik_TCA, 35, 2 },
- { &cik_TCC, 256, 16 },
+ { &cik_TCC, 256},
{ &cik_TD, 57, 16 },
{ &cik_TCP, 85, 16 },
{ &cik_GDS, 121 },
static void si_pc_emit_instance(struct si_context *sctx,
int se, int instance)
{
- struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
unsigned value = S_030800_SH_BROADCAST_WRITES(1);
if (se >= 0) {
static void si_pc_emit_shaders(struct si_context *sctx,
unsigned shaders)
{
- struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
radeon_set_uconfig_reg_seq(cs, R_036780_SQ_PERFCOUNTER_CTRL, 2);
radeon_emit(cs, shaders & 0x7f);
{
struct si_pc_block *sigroup = (struct si_pc_block *)group->data;
struct si_pc_block_base *regs = sigroup->b;
- struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
unsigned idx;
unsigned layout_multi = regs->layout & SI_PC_MULTI_MASK;
unsigned dw;
static void si_pc_emit_start(struct si_context *sctx,
struct r600_resource *buffer, uint64_t va)
{
- struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
- radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs, buffer,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
static void si_pc_emit_stop(struct si_context *sctx,
struct r600_resource *buffer, uint64_t va)
{
- struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
si_gfx_write_event_eop(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DATA_SEL_VALUE_32BIT,
{
struct si_pc_block *sigroup = (struct si_pc_block *)group->data;
struct si_pc_block_base *regs = sigroup->b;
- struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
unsigned idx;
unsigned reg = regs->counter0_lo;
unsigned reg_delta = 8;
struct si_pc_block *block = &blocks[i];
unsigned instances = block->instances;
- if (!strcmp(block->b->name, "IA")) {
- if (screen->info.max_se > 2)
- instances = 2;
- }
+ if (!strcmp(block->b->name, "CB") ||
+ !strcmp(block->b->name, "DB"))
+ instances = screen->info.max_se;
+ else if (!strcmp(block->b->name, "TCC"))
+ instances = screen->info.num_tcc_blocks;
+ else if (!strcmp(block->b->name, "IA"))
+ instances = MAX2(1, screen->info.max_se / 2);
si_perfcounters_add_block(screen, pc,
block->b->name,