struct radeon_cmdbuf *cs = sctx->gfx_cs;
si_cp_release_mem(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
- EOP_DST_SEL_MEM,
- EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
+ EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
EOP_DATA_SEL_VALUE_32BIT,
buffer, va, 0, SI_NOT_QUERY);
si_cp_wait_mem(sctx, va, 0, 0xffffffff, 0);