struct pipe_fence_handle **fence,
unsigned flags)
{
+ struct si_context *sctx = (struct si_context *)ctx;
+
+ if (sctx->b.rings.dma.cs) {
+ sctx->b.rings.dma.flush(sctx,
+ flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
+ }
+
si_flush(ctx, fence,
flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
}
sctx->atoms.cache_flush = &sctx->cache_flush;
sctx->atoms.streamout_begin = &sctx->b.streamout.begin_atom;
+ sctx->atoms.streamout_enable = &sctx->b.streamout.enable_atom;
switch (sctx->b.chip_class) {
case SI:
return HAVE_LLVM >= 0x0304 && (sscreen->b.chip_class < CIK ||
sscreen->b.info.drm_minor >= 35);
- case PIPE_CAP_TGSI_TEXCOORD:
- return 0;
-
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
- return 64;
+ return R600_MAP_BUFFER_ALIGNMENT;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
- return 256;
+ case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
+ return 4;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
return HAVE_LLVM >= 0x0305 ? 330 : 140;
- case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
- return 1;
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
case PIPE_CAP_CUBE_MAP_ARRAY:
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
case PIPE_CAP_TEXTURE_GATHER_SM5:
+ case PIPE_CAP_TGSI_TEXCOORD:
+ case PIPE_CAP_FAKE_SW_MSAA:
+ case PIPE_CAP_TEXTURE_QUERY_LOD:
return 0;
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
/* Texturing. */
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
- case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
- return 15;
+ return 15; /* 16384 */
+ case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
+ /* textures support 8192, but layered rendering supports 2048 */
+ return 12;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
- return 16384;
+ /* textures support 8192, but layered rendering supports 2048 */
+ return 2048;
/* Render targets. */
case PIPE_CAP_MAX_RENDER_TARGETS: